參數(shù)資料
型號: 21440
廠商: Intel Corp.
英文描述: Multiport 10/100Mb/s Ethernet Controller(多端口10/100Mb/s 以太網(wǎng)控制器)
中文描述: 多端口10/100Mb/s以太網(wǎng)控制器(多端口支持10/100Mbps以太網(wǎng)控制器)
文件頁數(shù): 35/92頁
文件大?。?/td> 1352K
代理商: 21440
21440 Multiport 10/100Mb/s Ethernet Controller
3-15
Register Descriptions
3.2.3.5
Transmit Threshold and Backoff Register
Packet transmission starts when the amount of data in the transmit FIFO is larger than or equal to
this threshold, or the entire packet enters onto the FIFO. The effective serial transmit threshold in
bytes is equal to 8 x TSD + 4. If the sum of the effective serial transmit threshold and the effective
FIFO bus transmit threshold (based upon FFO_TSHD<TTH>) is larger than 230 bytes,
transmission can begin before the effective serial transmit threshold is reached in order to prevent
deadlock. A value of 0 is not allowed.
Bit Name
Bit Number
Bit Description
BKL
7:4
Backoff limit.
This is the maximum number used in the retransmission time algorithm
following a collision. Lower numbers will cause faster retransmission times.
According to Ethernet standard, this value must be programmed to be 10
(decimal).
TSD
3:0
Packet transmission threshold.
Packet transmission starts when the amount of data in the transmit FIFO is
larger than or equal to the threshold, or the entire packet enters onto the FIFO.
The effective threshold in bytes is equal to 8
×
TSD + 4. If the sum of effective
serial threshold and the effective parallel threshold is larger than 230 bytes,
the transmission can start before threshold is reached to prevent deadlock. A
value
of
0
is not allowed.
Access Rules
Register access
R/W
Value after reset
A3H
Packet transmission
threshold
Effective threshold
(bytes)
Packet transmission
threshold
Effective threshold
(bytes)
0
not allowed
8
68
1
12
9
76
2
20
10
84
3
28
11
92
4
36
12
100
5
44
13
108
6
52
14
116
7
60
15
124
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