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參數(shù)資料
| 型號： | 21440 |
| 廠商： | Intel Corp. |
| 英文描述： | Multiport 10/100Mb/s Ethernet Controller(多端口10/100Mb/s 以太網(wǎng)控制器) |
| 中文描述： | 多端口10/100Mb/s以太網(wǎng)控制器（多端口支持10/100Mbps以太網(wǎng)控制器） |
| 文件頁數(shù)： | 24/92頁 |
| 文件大?。?/td> | 1352K |
| 代理商： | 21440 |
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Register Descriptions
3-4
21440 Multiport 10/100Mb/s Ethernet Controller
3.2.2.2
Interrupt Status Register
The interrupt status register handles information regarding events that cause an interrupt. A
specific event sets a bit if it was programmed to generate an interrupt in the interrupt enable
register (INT_EN).
Reading this register will reset all the bits, except for the TXER and RXEV bits. These bits are
reset only when the corresponding status register is read.
Bit Name
Bit Number
Bit Description
—
7
RESERVED
STOP
6
Port stop.
Indicates that transmit or receive path is in the stop state, following disable
programming in the port control register. If both transmit and receive paths
are programmed to be stopped, this bit is set when they both reach the stop
state.
OVFC
5
Counter overflow.
Indicates that at least one management counter has reached its highest
possible value (and is stuck there). The overflowed counter needs to be
reset to prevent further interrupt.
LNCH
4
Link change.
Indicates that a link change has occurred while working in SYM mode. The
actual link status is reported in the link status register.
TXER
3
Transmit error.
A logical OR bit for all the bits in the transmit error status register.
TXOK
2
Transmit OK.
Indicates successful packet transmission.
RXEV
1
Receive event.
A logical OR of all the bits in the receive status register. This bit is set only
after the packet is fully received by the chip.
RXOK
0
Receive OK.
Indicates that a packet has been received without error. This bit is set only
after the packet is fully transferred onto the chip.
Access Rules
Register access
R
Value after reset
00H
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