參數(shù)資料
型號(hào): 21440
廠商: Intel Corp.
英文描述: Multiport 10/100Mb/s Ethernet Controller(多端口10/100Mb/s 以太網(wǎng)控制器)
中文描述: 多端口10/100Mb/s以太網(wǎng)控制器(多端口支持10/100Mbps以太網(wǎng)控制器)
文件頁(yè)數(shù): 74/92頁(yè)
文件大?。?/td> 1352K
代理商: 21440
21440 Multiport 10/100Mb/s Ethernet Controller
7-7
21440 Timing Diagrams
7.1.13
Receive Ready (rxrdy) Control Timing
Figure 7-13
shows the receive ready (rxrdy) control timing.
rxrdy will asset a minimum of two cycles after the assertion of rxctl_l, provided the amount of data
in the receive FIFO meets the programmed threshold. rxrdy assertion must also be at least two
cycles after the deassertion of rxsel_l.
rxrdy deasserts two cycles after the assertion of rxsel_l.
7.1.14
Consecutive Transmit-Transmit Timing
Figure 7-14
shows the consecutive transmit-transmit timing.
Figure 7-13. Receive rxrdy Timing
A4918-01
clk
rxctl_l
rxrdy{n}
Port Number n
rxsel_l
fps[2:0]
Figure 7-14. Consecutive Transmit-Transmit Timing
相關(guān)PDF資料
PDF描述
21446 Net186-EVAL-KT? 24.9KB (PDF)
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