參數(shù)資料
型號(hào): 21440
廠商: Intel Corp.
英文描述: Multiport 10/100Mb/s Ethernet Controller(多端口10/100Mb/s 以太網(wǎng)控制器)
中文描述: 多端口10/100Mb/s以太網(wǎng)控制器(多端口支持10/100Mbps以太網(wǎng)控制器)
文件頁(yè)數(shù): 44/92頁(yè)
文件大?。?/td> 1352K
代理商: 21440
Register Descriptions
3-24
21440 Multiport 10/100Mb/s Ethernet Controller
3.3.2
Network Statistic Counters Access Rules
The network statistic counters access rules are as follows:
The counters can be accessed with a base address equal to 100H or 200H. Accessing the
counters with the 100H base address causes them to reset. Accessing them with the 200H will
not reset the counter.
Any of the counter bytes can be read without reading the other bytes. Only the accessed bytes
are reset (if accessed with the 100H base address).
The counters must be read from the lower to the upper bytes, in consecutive accesses.
The statistic counters are not writable.
Note:
Counter overflow causes it to remain fixed at the highest value it has reached.
Receive statistic counters are updated even upon receive FIFO overflow.
All the byte counters take CRC bytes into account, but exclude the framing bits in the packets.
3.4
Access Sequences
This section describes the initialization, mode change, and interrupt handling sequences for the
21440.
3.4.1
Initialization Sequence
Each 21440 port must be initialized according to the following sequence:
1. Disable the port and reset it by writing:
06h to the port control register (PORT_CTR), and then
01h to the same register
2. Initialize the port by writing to the relevant configuration and serial registers.
3. Enable port operation by writing a value of 18h to the port control register (PORT_CTR).
3.4.2
Mode Change Sequence
In order to change the 21440 working mode without impacting packet transfer, the following
sequence must be used:
1. Disable the port by writing a value of 00h to the port control register (PORT_CTR).
2. Wait until the port enters the stop state. The stop state entry may generate an interrupt if
enabled, and is reported by the stop bit in the interrupt status register (INT_STT<STOP>).
3. Change the configuration and serial register values.
4. Enable port operation by writing a value of 18h to the port control register (PORT_CTR).
Note:
The FIFO bus mode register (FFO_BUS) can only be updated by using the initialization sequence,
which will cause an interruption of packet transfer.
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