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參數(shù)資料
| 型號： | 21440 |
| 廠商： | Intel Corp. |
| 英文描述： | Multiport 10/100Mb/s Ethernet Controller(多端口10/100Mb/s 以太網(wǎng)控制器) |
| 中文描述： | 多端口10/100Mb/s以太網(wǎng)控制器（多端口支持10/100Mbps以太網(wǎng)控制器） |
| 文件頁數(shù)： | 61/92頁 |
| 文件大?。?/td> | 1352K |
| 代理商： | 21440 |
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Network Interface Operation
6-4
21440 Multiport 10/100Mb/s Ethernet Controller
6.4
MAC Transmit Operation
This section describes the transmit operation in detail, as supported by the 21440. Transmit
activities are registered into the network management registers, which are accessible through the
CPU port.
6.4.1
Transmit Initiation
After the transmit FIFO is adequately filled up to the programmed threshold level
(TX_TSHD_BOFF<TSD>), or after there is a full frame loaded into the transmit FIFO, the 21440
starts to encapsulate the frame. The transmit encapsulation is performed by the transmit controller,
which delays the actual transmission of the data onto the network until it has been idle for a
minimum interpacket gap (IPG) time.
6.4.2
Initial Deferral
The 21440 constantly monitors the line. Actual transmission of the data onto the network occurs
only if it has been idle for a 96-bit time period and any backoff time requirements have been
satisfied. In accordance with the standard, the 21440 begins to measure the IPG in full-duplex
mode from the tendeassertion, and from crs deassertion in half-duplex mode. Because CRS
deassertion is an asynchronous event, it may be necessary to adjust the IPG used by the 21440 in
half-duplex mode (depending on the MII or SYM physical-layer selection). Care should be taken to
maintain standards compliance if these fields are modified.
The IPG time includes two parts, IPS1 and IPS2:
IPS1 Time (60
–
bit time)
The 21440 monitors the network for an idle state. If a carrier is sensed on the serial line during
this time, the 21440 defers and waits until the line is idle again before restarting the IPS1 time
count. If a carrier is sensed during the first 40-bit time after transmission of the 21440, the
21440 does not defer (carrier sense inhibition period).
IPS2 Time (36
–
bit time)
The 21440 continues to count time even if a carrier has been sensed on the network, and thus
forces collisions on the network. This enables all network stations to fairly access the serial line.
6.4.3
Frame Encapsulation
The transmit data frame encapsulation stream includes the appending of the 56 preamble bits and the
SFD to the basic frame beginning, and the FCS to the basic frame end. The basic frame loaded from
the bus includes the destination address field, the source address field, the type/length field, and the
data field. If the data field length is shorter than 46 bytes, and padding as well as CRC appending are
not disabled (TX_PARAM<CRCD,PADD>), the 21440 pads the basic frame with the pattern 00 for
up to 46 bytes. At the end of the frame, the 21440 appends the FCS field if CRC appending is not
disabled. If during the beginning of the packet load, the txasis signal is asserted, the 21440 ignores the
programmed mode and transmits the frame without the padding and the FCS field.
In the MII mode, the transmit enable signal (ten{i}) is asserted together with the first preamble
byte transmission and is deasserted with the last CRC byte transmission.
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