參數(shù)資料
型號(hào)： 16LF628A
廠商： Microchip Technology Inc.
元件分類： 8位微控制器
英文描述： FLASH-Based 8-Bit CMOS Microcontrollers
中文描述： 基于閃存的8位CMOS微控制器
文件頁(yè)數(shù)： 89/168頁(yè)
文件大小： 3760K
代理商： 16LF628A
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2002 Microchip Technology Inc.
Preliminary
DS40044A-page 87
PIC16F627A/628A/648A
12.5.2
USART SYNCHRONOUS SLAVE
RECEPTION
The operation of the Synchronous Master and Mlave
modes is identical except in the case of the SLEEP
mode. Also, bit SREN is a don't care in Slave mode.
If receive is enabled, by setting bit CREN, prior to the
SLEEP
instruction, then a word may be received during
SLEEP. On completely receiving the word, the RSR
register will transfer the data to the RCREG register
and if enable bit RCIE bit is set, the interrupt generated
will wake the chip from SLEEP. If the global interrupt is
enabled, the program will branch to the interrupt vector
(0004h).
Follow these steps when setting up a Synchronous
Slave Reception:
1.
TRISB<1> bit needs to be set and TRISB<2> bit
cleared in order to configure pins RB2/TX/CK
and RB1/RX/DT as the Universal Synchronous
Asynchronous Receiver Transmitter pins.
2.
Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
3.
If interrupts are desired, then set enable bit
RCIE.
4.
If 9-bit reception is desired, then set bit RX9.
5.
To enable reception, set enable bit CREN.
6.
Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated, if
enable bit RCIE was set.
7.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
8.
Read the 8-bit received data by reading the
RCREG register.
9.
If any error occurred, clear the error by clearing
bit CREN.
TABLE 12-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
TABLE 12-12: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on all
other
RESETS
0Ch
PIR1
EEIF
CMIF
RCIF
TXIF
—
CCP1IF TMR2IF
TMR1IF
0000 -000
0000 -000
18h
RCSTA
SPEN
RX9
SREN CREN
ADEN
FERR
OERR
RX9D
0000 000x
0000 000x
19h
TXREG USART Transmit data register
0000 0000
0000 0000
8Ch
PIE1
EEIE
CMIE
RCIE
TXIE
—
CCP1IE TMR2IE TMR1IE
0000 -000
0000 -000
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 -010
99h
SPBRG Baud Rate Generator Register
0000 0000
0000 0000
Legend:
x
= unknown,
-
= unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Transmission.
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on all
other
RESETS
0Ch
PIR1
EEIF
CMIF
RCIF
TXIF
—
CCP1IF TMR2IF
TMR1IF
0000 -000
0000 -000
18h
RCSTA
SPEN
RX9
SREN CREN
ADEN
FERR
OERR
RX9D
0000 000x
0000 000x
1Ah
RCREG USART Receive data register
0000 0000
0000 0000
8Ch
PIE1
EEIE
CMIE
RCIE
TXIE
—
CCP1IE TMR2IE TMR1IE
0000 -000
0000 -000
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 -010
99h
SPBRG Baud Rate Generator Register
0000 0000
0000 0000
Legend:
x
= unknown,
-
= unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Reception.
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