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參數資料
| 型號： | 16LF628A |
| 廠商： | Microchip Technology Inc. |
| 元件分類： | 8位微控制器 |
| 英文描述： | FLASH-Based 8-Bit CMOS Microcontrollers |
| 中文描述： | 基于閃存的8位CMOS微控制器 |
| 文件頁數： | 113/168頁 |
| 文件大小： | 3760K |
| 代理商： | 16LF628A |
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2002 Microchip Technology Inc.
Preliminary
DS40044A-page 111
PIC16F627A/628A/648A
15.0
INSTRUCTION SET SUMMARY
Each PIC16F627A/628A/648A instruction is a 14-bit
word divided into an OPCODE which specifies the
instruction type and one or more operands which fur-
ther specify the operation of the instruction. The
PIC16F627A/628A/648A instruction set summary in
Table 15-2 lists
byte-oriented
,
bit-oriented
, and
lit-
eral and control
operations. Table 15-1 shows the
opcode field descriptions.
For
byte-oriented
instructions, 'f' represents a file
register designator and 'd' represents a destination
designator. The file register designator specifies which
file register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If 'd' is zero, the result is
placed in the W register. If 'd' is one, the result is placed
in the file register specified in the instruction.
For
bit-oriented
instructions, 'b' represents a bit field
designator which selects the number of the bit affected
by the operation, while 'f' represents the number of the
file in which the bit is located.
For
literal and control
operations, 'k' represents an
eight or eleven bit constant or literal value.
TABLE 15-1:
OPCODE FIELD
DESCRIPTIONS
The instruction set is highly orthogonal and is grouped
into three basic categories:
Byte-oriented
operations
Bit-oriented
operations
Literal and control
operations
All instructions are executed within one single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of an
instruction. In this case, the execution takes two
instruction cycles with the second cycle executed as a
NOP
. One instruction cycle consists of four oscillator
periods. Thus, for an oscillator frequency of 4 MHz, the
normal instruction execution time is 1
μ
s. If a
conditional test is true or the program counter is
changed as a result of an instruction, the instruction
execution time is 2
μ
s.
Table 15-2 lists the instructions recognized by the
MPASM assembler.
Figure 15-1 shows the three general formats that the
instructions can have.
All examples use the following format to represent a
hexadecimal number:
0xhh
where h signifies a hexadecimal digit.
FIGURE 15-1:
GENERAL FORMAT FOR
INSTRUCTIONS
Field
Description
f
Register file address (0x00 to 0x7F)
W
Working register (accumulator)
b
Bit address within an 8-bit file register
k
Literal field, constant data or label
x
Don't care location (= 0 or 1)
The assembler will generate code with x = 0. It is the
recommended form of use for compatibility with all
Microchip software tools.
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1
label
Label name
TOS
Top of Stack
PC
Program Counter
PCLATH Program Counter High Latch
GIE
Global Interrupt Enable bit
WDT
Watchdog Timer/Counter
TO
Time out bit
PD
Power-down bit
dest
Destination either the W register or the specified regis-
ter file location
[ ]
Options
( )
Contents
→
Assigned to
< >
Register bit field
∈
In the set of
italics
User defined term (font is courier)
Note 1:
Any unused opcode is reserved. Use of
any reserved opcode may cause unex-
pected operation.
2:
To maintain upward compatibility with
future PICmicro
products, do not use the
OPTION
and
TRIS
instructions.
Byte-oriented file register operations
13
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
OPCODE d f (FILE #)
Bit-oriented file register operations
OPCODE b (BIT #) f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
OPCODE k (literal)
k = 8-bit immediate value
OPCODE k (literal)
k = 11-bit immediate value
General
CALL
and
GOTO
instructions only
13
8
7
6
0
13
10 9
7
0
6
13
8 7
0
11 10
0
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