- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄368731 > 16F628 (Microchip Technology Inc.) CAT 5E CROSSOVER PATCH CORD CABLE BLUE 1 FT PDF資料下載
參數(shù)資料
| 型號(hào)： | 16F628 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | CAT 5E CROSSOVER PATCH CORD CABLE BLUE 1 FT |
| 中文描述： | 基于閃存的8位CMOS微控制器 |
| 文件頁(yè)數(shù)： | 93/168頁(yè) |
| 文件大小： | 3760K |
| 代理商： | 16F628 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)當(dāng)前第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 91
PIC16F627A/628A/648A
13.3
READING THE EEPROM DATA
MEMORY
To read a data memory location, the user must write the
address to the EEADR register and then set control bit
RD (EECON1<0>). The data is available, in the very
next cycle, in the EEDATA register; therefore it can be
read in the next instruction. EEDATA will hold this value
until another read or until it is written to by the user
(during a write operation).
EXAMPLE 13-1:
DATA EEPROM READ
13.4
WRITING TO THE EEPROM DATA
MEMORY
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDATA register. Then the user must follow a
specific sequence to initiate the write for each byte.
EXAMPLE 13-2:
DATA EEPROM WRITE
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this
code segment. A cycle count is executed during the
required sequence. Any number what is not equal to
the required cycles to execute the required sequence
will cause the data not to be written into the EEPROM.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware.
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. The EEIF bit in the
PIR1 registers must be cleared by software.
13.5
WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the Data
EEPROM should be verified (Example 13-3) to the
desired value to be written. This should be used in
applications where an EEPROM bit will be stressed
near the specification limit.
EXAMPLE 13-3:
WRITE VERIFY
13.6
PROTECTION AGAINST
SPURIOUS WRITE
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built in. On power-up, WREN is cleared. Also
when enabled, the Power-up Timer (72 ms duration)
prevents EEPROM write.
The write initiate sequence, and the WREN bit together
help prevent an accidental write during brown-out,
power glitch, or software malfunction.
BSF
MOVLW
MOVWF
BSF
MOVF
BCF
STATUS, RP0
CONFIG_ADDR
EEADR
EECON1, RD
EEDATA, W
STATUS, RP0
;Bank 1
;
;Address to read
;EE Read
;W = EEDATA
;Bank 0
R
S
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF INTCON, GIE
STATUS, RP0
EECON1, WREN
INTCON, GIE
55h
EECON2
AAh
EECON2
EECON1,WR
;Bank 1
;Enable write
;Disable INTs.
;
;Write 55h
;
;Write AAh
;Set WR bit
;begin write
;Enable INTs.
BSF
MOVF
BSF
STATUS, RP0;Bank 1
EEDATA, W
EECON1, RD ;Read the
;value written
;
;Is the value written (in W reg) and
;read (in EEDATA) the same
;
SUBWF EEDATA, W
BTFSS STATUS, Z
GOTO
WRITE_ERR
:
:
;
;Is difference 0
;NO, Write error
;YES, Good write
;Continue program
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 16M0 | PC SERIAL MODEM CBL 50 FT |
| 16M0B | APPLE IIC CABLE TO IWRTR MODEM |
| 16M0BC | KEYBD.EXT. MINI DIN 4 MM 6 FT |
| 16M0BS | KEYBD.EXT. MINI DIN 4 MM 10 FT |
| 16M0D | MINI DIN 8, MALE-MALE 10 FT. |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 16F630 | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:14-Pin FLASH-Based 8-Bit CMOS Microcontrollers |
| 16F684-I | 制造商:Microchip Technology Inc 功能描述: |
| 16F6H | 制造商:EDAL 制造商全稱:EDAL 功能描述:Silicon High Voltage Assembly |
| 16F6H1 | 制造商:EDAL 制造商全稱:EDAL 功能描述:Silicon High Voltage Assembly |
| 16F7674 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SMD TWEEZER HEAD |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。