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參數(shù)資料
| 型號： | 16F628 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | CAT 5E CROSSOVER PATCH CORD CABLE BLUE 1 FT |
| 中文描述： | 基于閃存的8位CMOS微控制器 |
| 文件頁數(shù)： | 33/168頁 |
| 文件大?。?/td> | 3760K |
| 代理商： | 16F628 |
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2002 Microchip Technology Inc.
Preliminary
DS40044A-page 31
PIC16F627A/628A/648A
5.0
I/O PORTS
The PIC16F627A/628A/648A have two ports, PORTA
and PORTB. Some pins for these I/O ports are multi-
plexed with alternate functions for the peripheral fea-
tures on the device. In general, when a peripheral is
enabled, that pin may not be used as a general pur-
pose I/O pin.
5.1
IPORTA and TRISA Registers
PORTA is an 8-bit wide latch. RA4 is a Schmitt Trigger
input and an open drain output. Port RA4 is multiplexed
with the T0CKI clock input. RA5
(1)
is a Schmitt Trigger
input only and has no output drivers. All other RA port
pins have Schmitt Trigger input levels and full CMOS
output drivers. All pins have data direction bits (TRIS
registers) which can configure these pins as input or
output.
A '1' in the TRISA register puts the corresponding out-
put driver in a High-impedance mode. A '0' in the
TRISA register puts the contents of the output latch on
the selected pin(s).
Reading the PORTA register reads the status of the
pins whereas writing to it will write to the port latch. All
write operations are read-modify-write operations. So a
write to a port implies that the port pins are first read,
then this value is modified and written to the port data
latch.
The PORTA pins are multiplexed with comparator and
voltage reference functions. The operation of these
pins are selected by control bits in the CMCON
(comparator control register) register and the VRCON
(voltage reference control register) register. When
selected as a comparator input, these pins will read
as '0's.
TRISA controls the direction of the RA pins, even when
they are being used as comparator inputs. The user
must make sure to keep the pins configured as inputs
when using them as comparator inputs.
The RA2 pin will also function as the output for the
voltage reference. When in this mode, the V
REF
pin is a
very high-impedance output. The user must configure
TRISA<2> bit as an input and use high-impedance
loads.
In one of the Comparator modes defined by the
CMCON register, pins RA3 and RA4 become outputs
of the comparators. The TRISA<4:3> bits must be
cleared to enable outputs to use this function.
EXAMPLE 5-1:
Initializing PORTA
FIGURE 5-1:
BLOCK DIAGRAM OF
RA0/AN0:RA1/AN1 PINS
Note 1:
RA5 shares function with V
PP
. When V
PP
voltage levels are applied to RA5, the
device will enter Programming mode.
2:
On RESET, the TRISA register is set to all
inputs. The digital inputs (RA<3:0>) are
disabled and the comparator inputs are
forced to ground to reduce current con-
sumption.
3:
TRISA<6:7> is overridden by oscillator
configuration. When PORTA<6:7> is
overridden, the data reads ‘0’ and the
TRISA<6:7> bits are ignored.
CLRF
PORTA
;Initialize PORTA by
;setting
;output data latches
;Turn comparators off and
;enable pins for I/O
;functions
MOVLW
MOVWF
0x07
CMCON
BCF
BSF
MOVLW
STATUS, RP1
STATUS, RP0;Select Bank1
0x1F
;Value used to initialize
;data direction
TRISA
;Set RA<4:0> as inputs
;TRISA<5> always
;read as ‘1’.
;TRISA<7:6>
;depend on oscillator
;mode
MOVWF
Data
Bus
Q
D
Q
CK
WR
PORTA
WR
TRISA
Data Latch
TRIS Latch
RD
TRISA
RD PORTA
Analog
I/O Pin
Q
D
Q
CK
Input Mode
(CMCON Reg.)
D
Q
EN
To Comparator
Schmitt Trigger
Input Buffer
V
DD
V
SS
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