
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 81
PIC16F627A/628A/648A
Follow these steps when setting up an Asynchronous
Reception:
1.
TRISB<1> bit needs to be set and TRISB<2> bit
cleared in order to configure pins RB2/TX/CK
and RB1/RX/DT as the Universal Synchronous
Asynchronous Receiver Transmitter pins.
2.
Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH. (Section 12.1).
3.
Enable the asynchronous serial port by clearing
bit SYNC, and setting bit SPEN.
4.
If interrupts are desired, then set enable bit
RCIE.
5.
If 9-bit reception is desired, then set bit RX9.
6.
Enable the reception by setting bit CREN.
7.
Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated if enable
bit RCIE was set.
8.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9.
Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
enable bit CREN.
TABLE 12-7:
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
all other
RESETS
0Ch
PIR1
EEIF
CMIF
RCIF
TXIF
—
CCP1IF TMR2IF TMR1IF
0000 -000 0000 -000
18h
RCSTA
RCREG USART Receive data registe
r
SPEN
RX9
SREN
CREN
ADEN
FERR
OERR
RX9D
0000 000x 0000 000x
1Ah
0000 0000 0000 0000
8Ch
PIE1
EEIE
CMIE
RCIE
TXIE
—
CCP1IE TMR2IE TMR1IE
0000 -000 0000 -000
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
99h
SPBRG Baud Rate Generator Register
0000 0000 0000 0000
Legend:
x
= unknown,
-
= unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception.