參數(shù)資料
型號： 16F628
廠商： Microchip Technology Inc.
英文描述： CAT 5E CROSSOVER PATCH CORD CABLE BLUE 1 FT
中文描述： 基于閃存的8位CMOS微控制器
文件頁數(shù)： 107/168頁
文件大?。?/td> 3760K
代理商： 16F628
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 105
PIC16F627A/628A/648A
14.5.1
RB0/INT INTERRUPT
External interrupt on RB0/INT pin is edge triggered:
either rising if INTEDG bit (OPTION<6>) is set, or fall-
ing, if INTEDG bit is clear. When a valid edge appears
on the RB0/INT pin, the INTF bit (INTCON<1>) is set.
This interrupt can be disabled by clearing the INTE
control bit (INTCON<4>). The INTF bit must be cleared
in software in the interrupt service routine before re-
enabling this interrupt. The RB0/INT interrupt can
wake-up the processor from SLEEP, if the INTE bit was
set prior to going into SLEEP. The status of the GIE bit
decides whether or not the processor branches to the
interrupt vector following wake-up. See Section 14.8
for details on SLEEP, and Figure 14-17 for timing of
wake-up from SLEEP through RB0/INT interrupt.
14.5.2
TMR0 INTERRUPT
An overflow (FFh
→
00h) in the TMR0 register will
set the T0IF (INTCON<2>) bit. The interrupt can
be
enabled/disabled
by
(INTCON<5>) bit. For operation of the Timer0 module,
see Section 6.0.
setting/clearing
T0IE
14.5.3
PORTB INTERRUPT
An input change on PORTB <7:4> sets the RBIF
(INTCON<0>) bit. The interrupt can be enabled/dis-
abled by setting/clearing the RBIE (INTCON<4>) bit.
For operation of PORTB (Section 5.2).
14.5.4
COMPARATOR INTERRUPT
See Section 10.6 for complete description of compara-
tor interrupts.
FIGURE 14-15:
INT PIN INTERRUPT TIMING
Note:
If a change on the I/O pin should occur
when the read operation is being executed
(starts during the Q2 cycle and ends before
the start of the Q3 cycle), then the RBIF
interrupt flag may not get set.
Q2
Q1
Q3
Q4
Q2
Q1
Q3
Q4
Q2
Q1
Q3
Q4
Q2
Q1
Q3
Q4
Q2
Q1
Q3
Q4
OSC1
CLKOUT
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
Interrupt Latency
PC
PC+1
PC+1
0004h
0005h
Inst (0004h)
Inst (0005h)
Dummy Cycle
Inst (PC)
Inst (PC+1)
Inst (PC-1)
Inst (0004h)
Dummy Cycle
Inst (PC)
—
Note
1:
2:
INTF flag is sampled here (every Q1).
Asynchronous interrupt latency = 3-4 Tcy. Synchronous latency = 3 Tcy, where Tcy = instruction cycle time. Latency
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
CLKOUT is available in RC and INTOSC Oscillator mode.
For minimum width of INT pulse, refer to AC specs.
INTF is enabled to be set anytime during the Q4-Q1 cycles.
3:
4:
5:
(1)
(1)
(4)
(5)
(2)
(3)
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