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參數(shù)資料
| 型號： | 16F628 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | CAT 5E CROSSOVER PATCH CORD CABLE BLUE 1 FT |
| 中文描述： | 基于閃存的8位CMOS微控制器 |
| 文件頁數(shù)： | 87/168頁 |
| 文件大?。?/td> | 3760K |
| 代理商： | 16F628 |
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2002 Microchip Technology Inc.
Preliminary
DS40044A-page 85
PIC16F627A/628A/648A
12.4.2
USART SYNCHRONOUS MASTER
RECEPTION
Once Synchronous mode is selected, reception is
enabled
by
setting
either
(RCSTA<5>) or enable bit CREN (RCSTA<4>). Data is
sampled on the RB1/RX/DT pin on the falling edge of
the clock. If enable bit SREN is set, then only a single
word is received. If enable bit CREN is set, the recep-
tion is continuous until CREN is cleared. If both bits are
set then CREN takes precedence. After clocking the
last bit, the received data in the Receive Shift Register
(RSR) is transferred to the RCREG register (if it is
empty). When the transfer is complete, interrupt flag bit
RCIF (PIR1<5>) is set. The actual interrupt can be
enabled/disabled by setting/clearing enable bit RCIE
(PIE1<5>). Flag bit RCIF is a read only bit which is
RESET by the hardware. In this case it is RESET when
the RCREG register has been read and is empty. The
RCREG is a double buffered register, (i.e., it is a two
deep FIFO). It is possible for two bytes of data to be
received and transferred to the RCREG FIFO and a
third byte to begin shifting into the RSR register. On the
clocking of the last bit of the third byte, if the RCREG
register is still full then overrun error bit OERR
(RCSTA<1>) is set. The word in the RSR will be lost.
The RCREG register can be read twice to retrieve the
two bytes in the FIFO. Bit OERR has to be cleared in
software (by clearing bit CREN). If bit OERR is set,
transfers from the RSR to the RCREG are inhibited, so
it is essential to clear bit OERR if it is set. The 9th
receive bit is buffered the same way as the receive
data. Reading the RCREG register, will load bit RX9D
enable
bit
SREN
with a new value, therefore it is essential for the user to
read the RCSTA register before reading RCREG in
order not to lose the old RX9D information.
Follow these steps when setting up a Synchronous
Master Reception:
1.
TRISB<1> bit needs to be set and TRISB<2> bit
cleared in order to configure pins RB2/TX/CK
and RB1/RX/DT as the Universal Synchronous
Asynchronous Receiver Transmitter pins.
2.
Initialize the SPBRG register for the appropriate
baud rate. (Section 12.1)
3.
Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
4.
Ensure bits CREN and SREN are clear.
5.
If interrupts are desired, then set enable bit
RCIE.
6.
If 9-bit reception is desired, then set bit RX9.
7.
If a single reception is required, set bit SREN.
For continuous reception set bit CREN.
8.
Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
enable bit RCIE was set.
9.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
10. Read the 8-bit received data by reading the
RCREG register.
11. If any error occurred, clear the error by clearing
bit CREN.
TABLE 12-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR
Value on all
other
RESETS
0Ch
PIR1
EEIF
CMIF
RCIF
TXIF
—
CCP1IF TMR2IF
TMR1IF
0000 -000
0000 -000
18h
RCSTA
SPEN
RX9
SREN CREN
ADEN
FERR
OERR
RX9D
0000 000x
0000 000x
1Ah
RCREG USART Receive data register
0000 0000
0000 0000
8Ch
PIE1
EEPIE
CMIE
RCIE
TXIE
—
CCP1IE TMR2IE TMR1IE
-000 0000
-000 -000
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 -010
99h
SPBRG Baud Rate Generator Register
0000 0000
0000 0000
Legend:
x
= unknown,
-
= unimplemented read as '0'. Shaded cells are not used for Synchronous Master Reception.
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