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參數(shù)資料
| 型號(hào)： | 16F628 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | CAT 5E CROSSOVER PATCH CORD CABLE BLUE 1 FT |
| 中文描述： | 基于閃存的8位CMOS微控制器 |
| 文件頁(yè)數(shù)： | 108/168頁(yè) |
| 文件大?。?/td> | 3760K |
| 代理商： | 16F628 |
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PIC16F627A/628A/648A
DS40044A-page 106
Preliminary
2002 Microchip Technology Inc.
TABLE 14-8:
SUMMARY OF INTERRUPT REGISTERS
14.6
Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key reg-
isters during an interrupt (e.g., W register and STATUS
register). This must be implemented in software.
Example 14-2 stores and restores the STATUS and W
registers. The user register, W_TEMP, must be defined
in a common memory location (i.e., W_TEMP is
defined at 0x70 in Bank 0 and is therefore, accessible
at 0xF0, 0x170 and 0x1F0). The Example 14-2:
Stores the W register
Stores the STATUS register
Executes the ISR code
Restores the STATUS (and bank select bit regis-
ter)
Restores the W register
EXAMPLE 14-2:
SAVING THE STATUS
AND W REGISTERS IN
RAM
14.7
Watchdog Timer (WDT)
The watchdog timer is a free running on-chip RC oscil-
lator which does not require any external components.
This RC oscillator is separate from the RC oscillator of
the CLKIN pin. That means that the WDT will run, even
if the clock on the OSC1 and OSC2 pins of the device
has been stopped, for example, by execution of a
SLEEP
instruction. During normal operation, a WDT
time out generates a device RESET. If the device is in
SLEEP mode, a WDT time out causes the device to
wake-up and continue with normal operation. The WDT
can be permanently disabled by programming the con-
figuration bit WDTE as clear (Section 14.1).
14.7.1
WDT PERIOD
The WDT has a nominal time out period of 18 ms (with
no prescaler). The time out periods vary with tempera-
ture, V
DD
and process variations from part to part (see
DC Specifications, Table 17-7). If longer time out peri-
ods are desired, a postscaler with a division ratio of up
to 1:128 can be assigned to the WDT under software
control by writing to the OPTION register. Thus, time
out periods up to 2.3 seconds can be realized.
The
CLRWDT
and
SLEEP
instructions clear the WDT
and the postscaler, if assigned to the WDT, and prevent
it from timing out and generating a device RESET.
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer time out.
14.7.2
WDT PROGRAMMING
CONSIDERATIONS
It should also be taken in account that under worst case
conditions (V
DD
= Min., Temperature = Max., max.
WDT prescaler) it may take several seconds before a
WDT time out occurs.
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR Reset
Value on all
other
RESETS
(1)
0Bh, 8Bh,
10Bh, 18Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
0Ch
PIR1
EEIF
CMIF
RCIF
TXIF
—
CCP1IF
TMR2IF
TMR1IF
0000 -000
0000 -000
8Ch
PIE1
EEIE
CMIE
RCIE
TXIE
—
CCP1IE TMR2IE TMR1IE
0000 -000
0000 -000
Note
1:
Other (non Power-up) Resets include MCLR Reset, Brown-out Reset and Watchdog Timer Reset during normal oper-
ation.
MOVWF W_TEMP
;copy W to temp register,
;could be in any bank
;swap status to be saved
;into W
;change to bank 0
;regardless of current
;bank
SWAPF STATUS,W
BCF
STATUS,RP0
MOVWF STATUS_TEMP ;save status to bank 0
;register
:
:(ISR)
:
SWAPF STATUS_TEMP,W;swap STATUS_TEMP register
;into W, sets bank to original
;state
MOVWF STATUS
;move W into STATUS register
SWAPF W_TEMP,F
;swap W_TEMP
SWAPF W_TEMP,W
;swap W_TEMP into W
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