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參數(shù)資料
| 型號(hào)： | 16F628 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | CAT 5E CROSSOVER PATCH CORD CABLE BLUE 1 FT |
| 中文描述： | 基于閃存的8位CMOS微控制器 |
| 文件頁(yè)數(shù)： | 101/168頁(yè) |
| 文件大?。?/td> | 3760K |
| 代理商： | 16F628 |
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2002 Microchip Technology Inc.
Preliminary
DS40044A-page 99
PIC16F627A/628A/648A
14.4.5
TIME OUT SEQUENCE
On power-up the time out sequence is as follows: First
PWRT time out is invoked after POR has expired. Then
OST is activated. The total time out will vary based on
oscillator configuration and PWRTE bit STATUS. For
example, in RC mode with PWRTE bit set (PWRT dis-
abled), there will be no time out at all. Figure 14-8,
Figure 14-9 and Figure 14-10 depict time out
sequences.
Since the time outs occur from the POR pulse, if MCLR
is kept low long enough, the time outs will expire. Then
bringing MCLR high will begin execution immediately
(see Figure 14-9). This is useful for testing purposes or
to synchronize more than one PIC16F627A/628A/
648A device operating in parallel.
Table 14-6 shows the RESET conditions for some spe-
cial registers, while Table 14-7 shows the RESET con-
ditions for all the registers.
14.4.6
POWER CONTROL (PCON) STATUS
REGISTER
The power control/STATUS register, PCON (address
8Eh) has two bits.
Bit0 is BOR (Brown-out Reset). BOR is unknown on
Power-on-Reset. It must then be set by the user and
checked on subsequent RESETS to see if BOR = 0
indicating that a brown-out has occurred. The BOR
STATUS bit is a don’t care and is not necessarily
predictable if the brown-out circuit is disabled (by
setting BOREN bit = 0 in the Configuration word).
Bit1 is POR (Power-on Reset). It is a ‘0’ on Power-on
Reset and unaffected otherwise. The user must write a
‘1’ to this bit following a Power-on Reset. On a subse-
quent RESET if POR is ‘0’, it will indicate that a Power-
on Reset must have occurred (V
DD
may have gone too
low).
TABLE 14-3:
TIME OUT IN VARIOUS SITUATIONS
TABLE 14-4:
STATUS/PCON BITS AND THEIR SIGNIFICANCE
Oscillator Configuration
Power-up
Brown-out Reset
Wake-up
from SLEEP
PWRTEN = 0
PWRTEN = 1
PWRTEN = 0
PWRTEN = 1
XT, HS, LP
72 ms +
1024T
OSC
1024T
OSC
72 ms +
1024T
OSC
1024T
OSC
1024T
OSC
RC, EC
72 ms
—
72 ms
—
—
INTOSC
72 ms
—
72 ms
—
6
μ
s
POR
BOR
TO
PD
Condition
0
X
1
1
Power-on Reset
0
X
0
X
Illegal, TO is set on POR
0
X
X
0
Illegal, PD is set on POR
1
0
X
X
Brown-out Reset
1
1
0
u
WDT Reset
1
1
0
0
WDT Wake-up
1
1
u
u
MCLR Reset during normal operation
1
1
1
0
MCLR Reset during SLEEP
Legend: u = unchanged, x = unknown.
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