參數(shù)資料
型號(hào): μPD705100
廠商: NEC Corp.
英文描述: 32 Bit Microprocessor(32 位微處理器)
中文描述: 32位微處理器(32位微處理器)
文件頁(yè)數(shù): 56/81頁(yè)
文件大?。?/td> 441K
代理商: ΜPD705100
56
V830
TM
USER'S MANUAL
(4) Burst write cycle
Burst write cycles are used to transfer data from built-in memory to a memory space in four-word
(16-byte) units. They cannot be used to access an I/O space.
The rising edge of the bus clock in the Ta state triggers the output of the address and the activation of
BCYST to signify the beginning of a bus cycle. For access to a space which involves chip select output,
CSn is also output at the same timing.
The bus then enters to the Tb1 state. In this state, the address is output as is and BCYST becomes inactive.
Also, the write data is output at the rising edge of the bus clock. READY is sampled at the rising edge
of the first bus clock after the end of the Tb1 state. If READY is inactive, the bus enters the Tb1 state
(wait) again. Thereafter, each time the Tb1 state ends, READY is sampled. When READY becomes
active, the bus enters the Tb2 state. In the Tb2 state, the address and write data are output on the rising
edge of the bus clock and READY is sampled at the same timing as in the Tb1 state. The same timing
also applies to the subsequent Tb3 to Tb8 states.
Figure 5-11. Burst Write Cycle (16-Bit Bus Mode)
Ta
Tb1
Tb2
Tb3
Tb4
Tb5
Tb6
Tb7
Tb8
BCLK (input)
Note 1
A1 (output)
BH (output)
D0-D15 (I/O)
CS0-CS3 (output)
Note 2
BCYST (output)
ST0-ST3 (output)
R/W (output)
READY (input)
A3 (output)
A2 (output)
Notes 1.
A4-A27 (output) and BE0-BE3 (output)
2.
If the chip select function is not used, A28-A31 are output to CS0-CS3.
Remarks 1.
A broken line indicates high impedance.
2.
An arrow indicates a sampling timing.
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