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參數(shù)資料
| 型號： | μPD705100 |
| 廠商： | NEC Corp. |
| 英文描述： | 32 Bit Microprocessor(32 位微處理器) |
| 中文描述： | 32位微處理器（32位微處理器） |
| 文件頁數(shù)： | 24/81頁 |
| 文件大小： | 441K |
| 代理商： | ΜPD705100 |
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24
V830
TM
USER'S MANUAL
ST3
ST2
ST1
ST0
R/W
Bus cycle type
Data size
0
0
0
0
0
I/O write
1/2/4 bytes
0
0
0
0
1
I/O read
1/2/4 bytes
0
0
0
1
RFU
0
0
1
0
Hald acknowledge
Notes 1 and 2
0
0
1
1
Stop acknowledge
Notes 1 and 2
0
1
RFU
1
0
0
0
0
RFU
1
0
0
0
1
Single instruction read
4 bytes
1
0
0
1
0
Single data write
1/2/4 bytes
1
0
0
1
1
Single data read
1/2/4 bytes
1
0
1
0
Idle state (with no external access request)
1
0
1
1
0
Bus lock write
4 bytes
1
0
1
1
1
Bus lock read
4 bytes
1
1
0
0
0
RFU
1
1
0
0
1
Instruction cache refill
16 bytes
1
1
0
1
0
RFU
1
1
0
1
1
Data cache refill
16 bytes
1
1
1
0
RFU
1
1
1
1
0
Block data write
16 bytes
1
1
1
1
1
Block data read
16 bytes
: Don’t care
Notes 1.
ST0-ST3 do not change at the time of internal memory access or internal I/O access.
2.
BCYST does not become active at hold acknowledge or stop acknowledge.
(8)
BCYST (Bus Cycle Start): tristate output
Outputs a signal indicating the start of a bus cycle. The pin is at the low level in the Ta state.
(9)
R/W (Read/Write): tristate output
Outputs a signal indicating whether the current bus cycle is a read or write cycle. The pin is valid only
during a bus cycle. It outputs a high-level signal during a read cycle and a low-level signal during a write
cycle. The pin changes in synchronization with the rise of a bus clock pulse in the Ta state.
(10) READY (Ready): input
Receives the signal for terminating a bus cycle. The signal is sampled at the rise of a bus clock pulse
at the end of the Ts, Tb1-Tb8, Tw1-Tw2 states.
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