參數(shù)資料
型號(hào)： μPD705100
廠商： NEC Corp.
英文描述： 32 Bit Microprocessor(32 位微處理器)
中文描述： 32位微處理器（32位微處理器）
文件頁(yè)數(shù)： 40/81頁(yè)
文件大小： 441K
代理商： ΜPD705100
40
V830
TM
USER'S MANUAL
(3) Burst read cycle
Burst read cycles are used to transfer data from a memory space to built-in memory in four-word (16-byte)
units. They cannot be used to access an I/O space.
The rising edge of the bus clock in the Ta state triggers the output of the address and the activation of
BCYST to signify the beginning of a bus cycle. For access to a space which involves chip select output,
CSn is also output at the same timing.
The bus then enters the Tb1 state. In this state, the address is output as is and BCYST becomes inactive.
READY is sampled at the rising edge of the first bus clock after the end of the Tb1 state. If READY is
inactive, the bus re-enters the Tb1 state (wait). Thereafter, each time the Tb1 state ends, READY is
sampled. Once READY becomes active, the rising edge of the bus clock triggers the sampling of the read
data, as well as transition to the Tb2 state. In the Tb2 state, the address is output at the rising edge of
the bus clock and READY and the read data are sampled at the same timing as in the Tb1 state. The
same timing also applies to the subsequent Tb3 and Tb4 states. An idle state (Ti) is always inserted
immediately after a burst read cycle.
Figure 4-6. Burst Read Cycle (32-Bit Bus Mode)
Ta
Tb1
Tb1
Tb2
Tb2
Tb3
Tb3
Tb4
Tb4
Ti
BCLK (input)
CS0-CS3 (output)
BCYST (output)
R/W (output)
READY (input)
Note 2
D0-D31 (I/O)
Note 1
A3 (Output)
A2 (Output)
ST0-ST3 (output)
Note 3
Notes 1.
A4-A27 (output) and BE0-BE3 (output)
2.
If the chip select function is not used, A28-A31 are output to CS0-CS3.
3.
Idle state
Remarks 1.
A broken line indicates high impedance.
2.
An arrow indicates a sampling timing.
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