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參數(shù)資料
| 型號： | μPD705100 |
| 廠商： | NEC Corp. |
| 英文描述： | 32 Bit Microprocessor(32 位微處理器) |
| 中文描述： | 32位微處理器（32位微處理器） |
| 文件頁數(shù)： | 54/81頁 |
| 文件大小： | 441K |
| 代理商： | ΜPD705100 |
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54
V830
TM
USER'S MANUAL
(2) Single write cycle
Single write cycles are classified into memory write and I/O write cycles. Between these two types of write
cycles, only the status signal (ST0-ST3) is different. Also, the timing differs slightly between byte/halfword
access and word access.
For byte/halfword access, the rising edge of the bus clock in the Ta state triggers the output of the address
and write data and the activation of BCYST to signify the beginning of a bus cycle. For access to a space
which involves chip select output, CSn is also output at the same timing.
The bus then enters the Ts state. In this state, the address and write data are output as is and BCYST
becomes inactive. READY is sampled at the first rising edge of the bus clock after the end of the Ts state.
If READY is inactive, the bus re-enters the Ts state (wait). Thereafter, each time the Ts state ends, READY
is sampled. The Ts state continues as long as READY is inactive.
For word access, the address and data are output at the rising edge of the bus clock in the Tw2 state.
Otherwise, Tw1 and Tw2 work for timing in the same way as Ts for byte/halfword access.
Figure 5-9. Single Write Cycle (16-Bit Bus Mode)
BCLK (input)
Note 1
A1 (output)
BH (output)
CS0-CS3 (output)
Note 2
BCYST (output)
D0-D15 (I/O)
R/W (output)
READY (input)
Ta
Ts
Ta
Tw1
Tw2
Notes 1.
A2-A27 (output), BE0-BE3 (output), and ST0-ST3 (output)
2.
If the chip select function is not used, A28-A31 are output to CS0-CS3.
Remarks 1.
A broken line indicates high impedance.
2.
An arrow indicates a sampling timing.
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