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參數(shù)資料
| 型號： | μPD705100 |
| 廠商： | NEC Corp. |
| 英文描述： | 32 Bit Microprocessor(32 位微處理器) |
| 中文描述： | 32位微處理器（32位微處理器） |
| 文件頁數(shù)： | 53/81頁 |
| 文件大?。?/td> | 441K |
| 代理商： | ΜPD705100 |
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53
CHAPTER 5 16-BIT BUS MODE
5.3.2 Memory Access and I/O Access
(1) Single read cycle
Single read cycles can be classified into memory read and I/O read cycles. Between these two types of
read cycles, only the status signal (ST0-ST3) is different. Also, the timing is differs slightly between
byte/halfword access and word access.
For byte/halfword access, the rising edge of the bus clock in the Ta state triggers the output of the address
and the activation of BCYST to signify the beginning of a bus cycle. For access to a space which involves
chip select output, CSn is also output at the same timing.
The bus then enters to the Ts state. In this state, the address is output as is and BCYST becomes inactive.
READY is sampled at the first rising edge of the bus clock after the end of the Ts state. If READY is inactive,
the bus re-enters the Ts state (wait). Thereafter, each time the Ts state ends, READY is sampled. The
Ts state continues for as long as READY is inactive.
Once READY becomes active, the read data will be sampled at the rising edge of the bus clock.
For word access, the address is output when the bus clock rises in the Tw2 state. Otherwise, Tw1 and
Tw2 work for timing the same way as Ts for byte/halfword access.
Immediately after a single read cycle, an idle state (Ti) is always inserted.
Figure 5-8. Single Read Cycle (16-Bit Bus Mode)
Ta
Ts
Ti
Ta
Tw1
Tw2
Ti
BCLK (input)
Note 1
A1 (output)
BH (output)
D0-D15 (I/O)
CS0-CS3 (output)
Note 2
BCYST (output)
ST0-ST3 (output)
R/W (output)
READY (input)
Note 3
Note 3
Notes
1.
A2-A27 (output) and BE0-BE3 (output)
2.
If the chip select function is not used, A28-A31 are output to CS0-CS3.
3.
Idle state
Remarks 1.
A broken line indicates high impedance.
2.
An arrow indicates a sampling timing.
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