參數(shù)資料
型號(hào)： μPD705100
廠商： NEC Corp.
英文描述： 32 Bit Microprocessor(32 位微處理器)
中文描述： 32位微處理器（32位微處理器）
文件頁(yè)數(shù)： 25/81頁(yè)
文件大?。?/td> 441K
代理商： ΜPD705100
25
CHAPTER 2 PIN FUNCTIONS
(11) HLDRQ (Hold Request): input
Receives a signal input to the CPU to request bus mastership. The signal is sampled at the rise of the
last of the Ts and Tb4 states (Ts, Tb8, and Tw2 in 16-bit bus mode) or at the rise of the Ti state.
(12) HLDAK (Hold Acknowledge): output
Outputs a signal acknowledging input to HLDRQ. The pin changes in synchronization with the rise of
a bus clock pulse.
The pin becomes active after the CPU relinquishes bus mastership, and D0-D31, BE0-BE3, ST0-ST3,
and R/W are set to high impedance from the next clock pulse until the pin changes to the high level. When
HLDRQ becomes inactive, the CPU makes HLDAK inactive and regains bus mastership.
(13) SIZ16B (Bus Size 16 bits): input
Receives a signal for fixing the external data bus width to 16 bits. When SIZ16B becomes active, the
CPU enters the mode in which signals corresponding to the 16-bit data bus system are output from BE0,
BE1, BH, and A1 and D16-D31 are set to high impedance. The signal is sampled at the rise of the first
bus clock pulse issued after RESET becomes high.
SIZ16B can be changed at reset only. If an attempt is made to change the pin at any other time, the
operation of the CPU cannot be guaranteed.
(14) NMI (Non-maskable Interrupt Request): input
Receives a nonmaskable interrupt request signal issued to the CPU. The signal is sampled at the rise
of a bus clock pulse, and the interrupt request is detected when NMI changes from high to low.
(15) INT (Interrupt Request): input
Receives a maskable interrupt request signal issued to the CPU. The signal at INT is sampled at the
rise of a bus clock pulse. The interrupt request is detected when the following three conditions are
satisfied:
(a) All of the NP, EP, and ID flags in PSW are set to 0.
(b) The interrupt level of INTV0-INTV3 is higher than the interrupt permit level for PSW.
(c) INT is active.
The V830 checks whether an interrupt request exists at the end of an instruction, or while it is not
performing internal processing. If an interrupt request is detected, the V830 accepts it.
INT must be held at the active level, together with INTV0-INTV3, until the CPU starts interrupt handling
and posts external notification, by software, that the interrupt request has been accepted.
(16) INTV0-INTV3 (Interrupt Level): input
Receive a maskable interrupt request signal, issued to the CPU. The signal at INTV0-INTV3 is sampled
at the rise of a bus clock pulse.
INTV0-INTV3 must be held at the active level, together with INT, until the CPU starts interrupt handling
and posts external notification, by software, that the interrupt request has been accepted. (The interrupt
level, however, can be changed to a higher priority.)
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