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參數(shù)資料
| 型號： | ZR36060 |
| 廠商： | Zoran Corporation |
| 元件分類： | Codec |
| 英文描述： | Integrated JPEG Codec(集成JPEG編解碼器) |
| 中文描述： | 綜合JPEG編解碼器（集成的JPEG編解碼器） |
| 文件頁數(shù)： | 9/46頁 |
| 文件大?。?/td> | 307K |
| 代理商： | ZR36060 |
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7
Integrated JPEG CODEC
UV7:UV0
I/O
In 16-bit video mode (Video8==0), these lines are the chrominance video lines. In compression these lines are inputs, while in
decompression they are outputs.
In 8-bit mode (Video8==1) these lines are not used: in compression they are ignored (inputs), and in decompression they are
floating.
During and after RESET this bus is floating with internal pull-ups.
VCLKx2
I
Main Video Clock input. The video interface of the ZR36060 is synchronized by this clock.
VCLK
I
Digital video bus clock enable. Used as a qualifier of the video bus data. Must be synchronized and toggling at half the frequen-
cy of VCLKx2, in both 8 and 16-bit video bus width modes.
HSYNC
I/O
Horizontal sync. When the ZR36060 is slave (SyncMstr==0), HSYNC is input, and when it is the sync master (SyncMstr==1)
HSYNC is an output.
During and after RESET this pin is floating (input mode).
VSYNC
I/O
Vertical sync. When the ZR36060 is slave (Syncstr==0), VSYNC is input, and when it is the sync master (SyncMstr==1) VSYNC
is an output.
During and after RESET this pin is floating (input mode).
FI
I/O
Digital video bus field indicator (odd/even). When the ZR36060 is the master of the video bus FI is an output, otherwise it is an
input. The polarity of FI, as input or output, is set by FiPol.
During and after RESET this pin is floating (input mode).
BLANK
O
Digital video bus composite blank output. Active only when the ZR36060 is the sync master of the video bus, otherwise the pin
is floating. The horizontal and vertical blanking areas are programmable.
During and after RESET this pin is floating with internal pullup.
PVALID
I
When the ZR36060 is in compression mode, this input is used as an additional qualifier (other than VCLK) of the video data
signals and the sync signals. An active level sampled on this signal at the time when a pixel is sampled, indicates that this is a
valid pixel. This input is meant to be connected to the PXEN output of the ZR36057.
When the ZR36060 is in decompression mode, this input is used by the recipient of the video to stall the video stream of the
ZR36060. A non-active level sampled on this signal will cause the ZR36060 to continue to output the current pixel instead of
proceeding to the next one. Once PVALID is sampled active again the normal pixel sequence resumes.
If the ZR36060 is the video sync master, then PVALID not active will freeze the internal sync generator. The polarity of PVALID
can be programmed.
SUBIMG
O
This output dynamically indicates the boundaries of a sub-image rectangle within the main input or output field size. When the
pixels within the programmable rectangle are output/input, SUBIMG is active. For a sub-line of consecutive pixels within the
rectangle, SUBIMG is continuously active. The polarity of SUBIMG is programmable.
SUBIMG may be connected to the FEIN input of the SAA7110/11, or the read-enable input of a line buffer, FIFO, etc., to permit
pixel-by-pixel video mixing during compression and decompression.
During and after RESET this pin is logic high.
POE
I
Pixel Output Enable. Used to disable the video bus during decompression, to permit pixel-by-pixel video mixing of the ZR36060
video output with another source. It can be directly connected to the SUBIMG output, or to other suitable control.
Control & Status (10 pins)
RESET
I
Reset. When this input is asserted the ZR36060 goes into its RESET state. When it is deasserted all state machines are in
IDLE mode and registers contain their default values. RESET must be active for at least 8 VCLKx2 cycles.
SLEEP
I
Power-down mode. When this input is active (low), the ZR36060 goes into its SLEEP (power-down) mode, discontinuing all
chip operation and consuming minimal supply current.
This pin also initiates coarse locking of the internal PLL to the VCLKx2 frequency. It must be toggled at least once after RESET.
SLEEP must remain low for at least 8 VCLKx2 cycles.
END
O
End of process indication. This active-low output signal indicates completion of a field compression/decompression process.
During and after RESET
this pin is logic low.
EOI
O
End-of-image marker indication. This active-low output signal indicates the last code byte, or word (FFD8 code) is being output
or input. EOI is deasserted together with the deassertion (rising edge) of END upon beginning of the next field process.
During and after RESET this pin is logic low.
START
I
Start compression/decompression command input. When the ZR36060 is in IDLE state, it looks for an active low level on this
input in order to start compression or decompression. Once the active level is sampled the ZR36060 will start compression or
decompression with the next VSYNC or with the next odd VSYNC (depending on the FRAME input).
To be detected correctly, START must remain low for at least 2 VCLKs.
When the ZR36060 is connected to the ZR36057, this input must be connected to a GCS output of the ZR36057.
FRAME
I
This input is sampled by the ZR36060 together with the START input. When START is sampled active, then if FRAME is also
active the ZR36060 will start compressing/decompressing at the next odd field. Otherwise it will start with the next field.
Table 1: Pin Descriptions (Continued)
Symbol
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZR36060 | Circular Connector; No. of Contacts:19; Series:; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:14; Circular Contact Gender:Socket; Circular Shell Style:Cable Receptacle; Insert Arrangement:14-19 |
| ZR36060PQC | Integrated JPEG CODEC |
| ZR36067 | AV PCI CONTROLLER |
| ZR36067PQC | AV PCI CONTROLLER |
| ZR36067 | PCI Adapter Intended for Multimedia Applications on PCI Systems(PCI（外圍部件互連）適配器（用于PCI系統(tǒng)的多媒體）) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZR36060PQC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Integrated JPEG CODEC |
| ZR36060PQC-27 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| ZR36060PQC-29.5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| ZR36067 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:AV PCI CONTROLLER |
| ZR36067PQC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:AV PCI CONTROLLER |
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