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參數(shù)資料
| 型號： | ZR36060 |
| 廠商： | Zoran Corporation |
| 元件分類： | Codec |
| 英文描述： | Integrated JPEG Codec(集成JPEG編解碼器) |
| 中文描述： | 綜合JPEG編解碼器（集成的JPEG編解碼器） |
| 文件頁數(shù)： | 29/46頁 |
| 文件大小： | 307K |
| 代理商： | ZR36060 |
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Integrated JPEG CODEC
7.0 POWER MANAGEMENT AND POWER-UP
The ZR36060 has two power consumption modes: the normal
mode, and a low-power mode, called the SLEEP state, achieved
by activating the SLEEP pin. This power saving is achieved by
disabling the internal clocking to all flip-flops and gates, so this
mode can be seen as a frozen state of the ZR36060. All outputs
retain their states, and bidirectional signals remain in their last
direction status
Transitions to or from the SLEEP state must be done via the
IDLE state. No host accesses are allowed in the SLEEP state,
and during the IDLE - SLEEP transition. Otherwise the ZR36060
must be reset again.
After the SLEEP pin is de-activated, the ZR36060 is operational
again, without the need for a reset, retaining all registers,
markers and parameters previously loaded. Before START can
be activated again for the next compression or decompression,
the host must write the Load bit.
Deactivation of SLEEP also serves to initiate the coarse frequen-
cy lock procedure of the internal PLL. It is mandatory to pulse
SLEEP after power-up, when the system clock (VCLKx2) is
setup and stable (within 10% of its nominal frequency). The
coarse lock must be initiated (using the SLEEP pin) each time
the system changes the frequency of VCLKx2 frequency, for
example if the video standard is changed. See Figure 39.
The coarse PLL frequency lock procedure takes 5000 VCLKx2
cycles, and is executed every low-to-high transition of SLEEP.
The ZR36060 remains in the SLEEP state during this time
interval.
Figure 39. Power-Up Sequence and SLEEP Operation
RESET
SLEEP
_state
VCC
Power On
RESET
(SLEEP must
be inactive)
(8 VCLKx2
min)
WAIT VCLKx2
INITIALIZED
& STABLE
(board config)
SLEEP
LOCK
IDLE
(operational)
RESET Period: Minimum pulse of 8 VCLKx2 cycles.
WAIT Period: Depend of system properly initialize the VCLKx2 to correct
operating frequency.
SLEEP Pulse: Minimum pulse of 8 VCLKx2 cycles.
LOCK Period After SLEEP deasserted, system must wait 5,000 VCLKx2 cycles
until the ZR36060 is correctly locked to the clock frequency.
IDLE: The ZR36060 is ready for operation.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZR36060 | Circular Connector; No. of Contacts:19; Series:; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:14; Circular Contact Gender:Socket; Circular Shell Style:Cable Receptacle; Insert Arrangement:14-19 |
| ZR36060PQC | Integrated JPEG CODEC |
| ZR36067 | AV PCI CONTROLLER |
| ZR36067PQC | AV PCI CONTROLLER |
| ZR36067 | PCI Adapter Intended for Multimedia Applications on PCI Systems(PCI（外圍部件互連）適配器（用于PCI系統(tǒng)的多媒體）) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZR36060PQC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Integrated JPEG CODEC |
| ZR36060PQC-27 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| ZR36060PQC-29.5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| ZR36067 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:AV PCI CONTROLLER |
| ZR36067PQC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:AV PCI CONTROLLER |
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