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參數(shù)資料
| 型號(hào)： | ZR36060 |
| 廠商： | Zoran Corporation |
| 元件分類： | Codec |
| 英文描述： | Integrated JPEG Codec(集成JPEG編解碼器) |
| 中文描述： | 綜合JPEG編解碼器（集成的JPEG編解碼器） |
| 文件頁數(shù)： | 11/46頁 |
| 文件大?。?/td> | 307K |
| 代理商： | ZR36060 |
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9
Integrated JPEG CODEC
FIVedge - Defines at which VSYNC edge the FI signal
changes state (leading or trailing edge). This is also the reset
point for the vertical counters, indicating the end of the previ-
ous field and the beginning of a new field.
After the parameters are properly initialized and loaded (using
the Load command), the sync generator is free running, and is
not affected by the state of the JPEG codec. The SyncRst
register bit resets the sync generator counters and the PVALID
signal can temporarily freeze the counting and sync signals.
3.1.2 Slave mode
When configured as a sync Slave, the ZR36060 samples the fol-
lowing signals:
HSYNC - Horizontal sync
VSYNC - Vertical sync
FI - Even/Odd field indication
The parameters Vtotal, Htotal, VsyncSize, HsyncSize, BVstart,
BVend, BHstart, BHend, BlPol, FIPol are not used in Slave
mode. VSPol, HSPol, FIDet and FIVedge are used as follows:
VSPol - Polarity of the VSYNC input signal.
HSPol - Polarity of the HSYNC input signal.
FIDet - Exchange the even/odd field interpretation after de-
tection. (detection can be accomplished in two ways
according to the FIExt parameter, see below)
FIVedge - Defines the reset point for the vertical counters in-
dicating the end of the previous field and the beginning of a
new field. When FIExt = 0 it also defines the proper VSYNC
edge used to latch HSYNC to internally detect the even/odd
field.
The field detection can be accomplished in two ways depending
on the FIExt parameter (see Figure 4):
External indication by means of the FI signal (FIExt = 1), tog-
gling at the VSYNC rate, indicating whether the current field
is even or odd. The polarity of FI is programmable, using the
FIPol parameter, while the even/odd interpretation can be
exchanged using the FIDet parameter.
Internal detection (FIExt = 0), derived from latching the state
of HSYNC at each VSYNC. This is useful when using the
ZR36060 with video sources that do not provide a dedicated
field indication signal. Odd fields are those where the
VSYNC edge latches the HSYNC during its short sync peri-
od, while on even fields the VSYNC edge latches the
HSYNC in the middle of the line (see Figure 4). The VSYNC
edge (leading or trailing) used to latch the HSYNC signal can
be programmed by means of the FIVedge parameter.
Changing FIDet will change the even/odd interpretation.
Note: the HSYNC edge must precede the latching VSYNC edge
by at least 2 VCLKs for reliable latching.
3.2 Data Formats
When the ZR36060 is configured for 16-bit video bus width
(Video8==0), the luminance signal is on Y7:0, and the chromi-
nance signals are multiplexed on the UV7:0 lines (see Figure 5).
When operating in 8-bit video bus mode (Video8==1), both the
luminance and the chrominance signals are on Y7:0, multiplexed
in time according to the CCIR656 recommendation (U=Cb,
V=Cr):
U0,Y0,V0,Y1,U2,Y2,V2,Y3,....
For 16-bit video, the pixels are sampled on every other rising
edge of VCLKx2, which is enabled by VCLK, the video clock
qualifier. The polarity of the VCLK qualifier is programmable via
the VCLKPol parameter. 8-bit video is sampled using all rising
edges of VCLKx2, at twice the pixel rate.
Note that 1 pixel length is always 1 VCLK, with both 16-bit and
8-bit video. All internal counters and video events are based on
VCLK, that must always be present (at half the frequency of
VCLKx2) even when the video interface is configured for 8-bit
width.
In decompression, the output pixel levels are CCIR-
601compliant, with values in the [16,235] range. It is possible to
override this and let the ZR36060 output the full 256-level scale
with the Range parameter bit.
Htotal
V
ODD Field
EVEN Field
VsyncSize
VSYNC
BVstart
BVend
BLANK
FI
Note: In this example VSPol = HSPol = FIPol = BlPol = FIVedge = 0.
HSYNC
HsyncSize
BLANK
BHstart
BHend
Figure 3. Video Sync Generation
Note: VSPol = HSPol = FIPol = FIDet = 0, FIVedge = 1
Figure 4. Field Detection Showing Hor. and Ver. Timing
HSYNC
VSYNC
FI
HSYNC
VSYNC
FI
ODD Field (Fields (1, 3, 5…)
EVEN Field (Fields (2, 4, 6…)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZR36060 | Circular Connector; No. of Contacts:19; Series:; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:14; Circular Contact Gender:Socket; Circular Shell Style:Cable Receptacle; Insert Arrangement:14-19 |
| ZR36060PQC | Integrated JPEG CODEC |
| ZR36067 | AV PCI CONTROLLER |
| ZR36067PQC | AV PCI CONTROLLER |
| ZR36067 | PCI Adapter Intended for Multimedia Applications on PCI Systems(PCI（外圍部件互連）適配器（用于PCI系統(tǒng)的多媒體）) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZR36060PQC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Integrated JPEG CODEC |
| ZR36060PQC-27 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| ZR36060PQC-29.5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| ZR36067 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:AV PCI CONTROLLER |
| ZR36067PQC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:AV PCI CONTROLLER |
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