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參數(shù)資料
| 型號： | ZR36060 |
| 廠商： | Zoran Corporation |
| 元件分類： | Codec |
| 英文描述： | Integrated JPEG Codec(集成JPEG編解碼器) |
| 中文描述： | 綜合JPEG編解碼器（集成的JPEG編解碼器） |
| 文件頁數(shù)： | 16/46頁 |
| 文件大?。?/td> | 307K |
| 代理商： | ZR36060 |
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14
Integrated JPEG CODEC
4.0 HOST INTERFACE
The host interface is a generic interface with an 8-bit bidirectional
data bus, 2-bit address bus (that indirectly maps a 1Kbyte
internal memory space), RD, WR, CS, and ACK pins. It supports
glueless interface to most microprocessors, microcontrollers,
and buses like the ISA.
When the Code interface is configured in Slave mode (see
section 5.0 “Code Interface”) some of the ZR36060 Host inter-
face pins have dual functions, as can be seen in Figure 15:
In this example SImgPol = SImgDat = VCLKPol = 0.
In this example SUBIMG is connected to POE to float the ZR36060 video bus.
SUBIMG changes state with resolution of one VCLK and at the rising edge of VCLKx2, in both 8-bit and 16-bit mode.
In 8-bit mode, the first pixel is enabled 2 VCLKx2 after SUBIMG changes state, and the last pixel is disabled 1 VCLKx2
after SUBIMG changes.
In 16-bit mode, the first pixel is enabled 3 VCLKx2 after SUBIMG changes state (this causes the first pixel from the
ZR36060 appear on the bus for 0.5 VCLK instead of a complete VCLK period). The last pixel is disabled 1 VCLKx2 after
SUBIMG changes, to avoid contention. This timing was chosen to match the characteristics of the SAA7110.
Figure 14. SUBIMG and POE timing during decompression, shown for 8- and 16-bit video
VCLKx2
VCLK
Y[7:0] from ZR36060
SUBIMG (POE)
8-Bit Video Interface
1
2
3
4
5
6
7
8
9
10
11
U2
Y2
12
13
2 VCLKx2
Y[7:0] External
u0
y0
v4
y5
u6
16-Bit Video Interface
Y[7:0] from ZR36060
UV[7:0] from
ZR36060
SUBIMG (POE)
Y[7:0] External
(SAA7110)
UV[7:0] External
(SAA7110)
Notes:
V2
Y3
U4
1 VCLKx2
y6
Y2
Y3
U2
V2
3 VCLKx2
1 VCLKx2
Sampled by
SAA7110
Sampled by
SAA7110
y0
y1
y5
y6
u0
v1
v4
u6
1.
2.
3.
4.
5.
CODE[7:0]
CCS
COE
CWE
CBUSY
ACK
CS
WR
RD
DATA[7:0]
ADDR[1:0]
ZR36060
a) Code Master Mode, 8-Bit Code Bus
Figure 15. The Various Code Interface Modes and the Host Interface
Code Only
Host Only
CBUSY
ACK
CS
WR
RD
DATA[7:0]
ADDR[1:0]
ZR36060
b) Code Slave Mode, 8-Bit Code Bus
Code/Host
Shared
CODE[7:0]
CBUSY
ACK
CS
WR
RD
DATA[7:0]
ADDR[1:0]
ZR36060
c) Code Slave Mode, 16-Bit Code Bus
Code
(Data Bus
Extension)
Code
Code/Host
Shared
相關PDF資料 |
PDF描述 |
|---|---|
| ZR36060 | Circular Connector; No. of Contacts:19; Series:; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:14; Circular Contact Gender:Socket; Circular Shell Style:Cable Receptacle; Insert Arrangement:14-19 |
| ZR36060PQC | Integrated JPEG CODEC |
| ZR36067 | AV PCI CONTROLLER |
| ZR36067PQC | AV PCI CONTROLLER |
| ZR36067 | PCI Adapter Intended for Multimedia Applications on PCI Systems(PCI（外圍部件互連）適配器（用于PCI系統(tǒng)的多媒體）) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ZR36060PQC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Integrated JPEG CODEC |
| ZR36060PQC-27 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| ZR36060PQC-29.5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| ZR36067 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:AV PCI CONTROLLER |
| ZR36067PQC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:AV PCI CONTROLLER |
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