- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373821 > ZR36060 (Zoran Corporation) Integrated JPEG Codec(集成JPEG編解碼器) PDF資料下載
參數(shù)資料
| 型號： | ZR36060 |
| 廠商： | Zoran Corporation |
| 元件分類： | Codec |
| 英文描述： | Integrated JPEG Codec(集成JPEG編解碼器) |
| 中文描述： | 綜合JPEG編解碼器（集成的JPEG編解碼器） |
| 文件頁數(shù)： | 30/46頁 |
| 文件大?。?/td> | 307K |
| 代理商： | ZR36060 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁當(dāng)前第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁
28
Integrated JPEG CODEC
8.0 REGISTER AND MEMORY DESCRIPTION
The ZR36060 internal memory space is implemented as 1024
bytes of RAM, accessible by the host controller through the host
interface. The contents of this RAM may be loaded into the final
storage registers and tables using the Load command (refer to
6.4 “Loading Parameters and Tables”). Figure 40 depicts the
partitioning of the RAM.
A “default” is specified for each register bit. This is its value after
reset.
8.1 General Control Registers
LOAD Parameters Register
Address 0x000
SyncRst:
Resets the video sync generator.
0
- No reset
1
- Reset the syncs. Start horizontal/vertical counting from 0, 0. The Sync Gen-
erator is maintained in reset state until the host writes 0 again to this bit.
Load:
Load all the internal memory parameters (including tables) to the respective
ZR36060 internal blocks. After writing Load = 1, the ZR36060 sets the Busy bit until
the load is complete and the ZR36060 is ready to operate. The Load bit must be
set every time a new parameter is written anywhere in the internal memory.
0
- No effect
1
- Load parameters now
Code FIFO Status Register (Read only)
Address 0x001
CFIFO[1:0]:
Indicates the fullness of the Code FIFO (ready only bits):
00 - less than 1/4 of the Code FIFO is occupied.
01 - less than 1/2 but more than (or exactly) 1/4 is occupied.
10 - less than 3/4 but more than (or exactly) 1/2 is occupied.
11 - more than (or exactly) 3/4 of the Code FIFO is occupied.
These bits are valid only when EOI is not asserted.
CBUSY:
Indicate the full/empty condition of the code FIFO (read only bit - identical
to CBUSY pin state, inverse logic)
0
- code FIFO not full / not empty
1
- code FIFO full / empty
This bit is valid only when CBUSY is an output; i.e.- in code slave mode.
Busy:
Status of the Load operation. The internal load of parameters can take
~100 microseconds. The host must poll this bit to know when the ZR36060 is ready
(not Busy) to load a new parameter set or start a compression/decompression
process.
0
- ZR36060 is ready to operate, no Load operation in progress
1
- Load is in progress now, don’t access any internal memory location while
this bit is set
Code Interface Register
Address 0x002
CodeMstr:
The ZR36060 is the Master or Slave of the Code bus
0
- Code Slave mode
1
- Code Master mode
CFIS:
Only in Master mode, defines the number of clocks for each code byte
transfer. Must be 0 in Code Slave mode.
0
- one VCLKx2 cycle
1
- two VCLKx2 cycles
Endian:
Defines the byte ordering when using 16-bit code slave interface. Must be
0 in Master mode or 8-bit Slave mode.
0
- first byte (‘FF’ of ‘FFD8’ SOI code) is on DATA[7:0] bus
1
- first byte (‘FF’ of ‘FFD8’ SOI code) is on CODE[7:0] bus
Code16:
Defines the code bus width for slave mode only. Must be 0 in Master
mode.
0
- 8-bit code bus
1
- 16-bit code bus
Figure 40. Internal Memory Map
000h
022h
030h
052h
060h
3FFh
Codec
Control Registers
Debug (Testing)
Video Registers
Spare
JPEG Markers Array
1
8 Bits Data
Host Address
Host Data
Host Interface
0x000
type
default
7
6
5
4
3
2
1
0
Load
RW
0
0
SyncRst
RW
0
X
X
X
X
X
X
0x001
type
default
7
6
5
4
3
2
1
0
Busy
RW
0
0
CFIFO0
RW
0
X
X
X
X
X
X
CBUSY
RW
CFIFO1
RW
0x002
type
default
7
6
5
4
0
3
2
1
0
–
0
Code16
RW
0
CodeMstr
RW
1
X
X
X
X
X
X
CFIS
RW
Endian
RW
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZR36060 | Circular Connector; No. of Contacts:19; Series:; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:14; Circular Contact Gender:Socket; Circular Shell Style:Cable Receptacle; Insert Arrangement:14-19 |
| ZR36060PQC | Integrated JPEG CODEC |
| ZR36067 | AV PCI CONTROLLER |
| ZR36067PQC | AV PCI CONTROLLER |
| ZR36067 | PCI Adapter Intended for Multimedia Applications on PCI Systems(PCI（外圍部件互連）適配器（用于PCI系統(tǒng)的多媒體）) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZR36060PQC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Integrated JPEG CODEC |
| ZR36060PQC-27 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| ZR36060PQC-29.5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| ZR36067 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:AV PCI CONTROLLER |
| ZR36067PQC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:AV PCI CONTROLLER |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。