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參數(shù)資料
| 型號： | ZR36060 |
| 廠商： | Zoran Corporation |
| 元件分類： | Codec |
| 英文描述： | Integrated JPEG Codec(集成JPEG編解碼器) |
| 中文描述： | 綜合JPEG編解碼器（集成的JPEG編解碼器） |
| 文件頁數(shù)： | 34/46頁 |
| 文件大?。?/td> | 307K |
| 代理商： | ZR36060 |
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32
Integrated JPEG CODEC
Sync Generator Registers
Address: 0x036 - 0x041
Parameters used by the internal video sync generator when it is in Master mode
(SyncMstr=1).
Horizontal measures are in number of VCLKs (1 VCLK = 1 pixel, regardless of t
video bus width), from the leading edge of HSYNC.
Vertical measures are in number of HSYNCs (1 HSYNC = 1 line), from the leading
or trailing edge of VSYNC according to the FIVedge parameter.
BLANK signal window parameters are relative to a different horizontal/vertical
origin than the SUBIMG and ACTIVE video windows.
Vtotal[15:0]:
Number of horizontal lines per frame. Writing N indicates that the
frame has N+1 total lines. (e.g. - Vtotal = 524, for NTSC, 525 lines per frame)
Maximum permitted value is 65535.
Htotal[9:0]:
Number of total VCLKs (pixels) per line. Write N indicate that the line
has N+1 pixels. (e.g. - Htotal = 857, for NTSC-CCIR 858-pixels per line)
Maximum permitted value is 768.
VsyncSize[7:0]:
Length of VSYNC pulse measured in number of lines. Writing N
indicates that the sync pulse has N+1 lines. (e.g. - VsyncSize = 5, for 6-lines
vertical sync interval)
HsyncSize[7:0]:
Length of HSYNC pulse measured in number of VCLKs (pixels).
Writing N indicates that the sync pulse has N+1 pixels. (e.g. - HsyncSize = 31, for
32-pixels horizontal sync interval)
BVstart[7:0]:
Length from VSYNC edge to first. non-BLANK line measured in
number of lines. Writing N indicates that the first non-BLANK line is line N+1. (e.g.
- BVstart = 11, to have the first non-BLANK line on line number 12)
BHstart[7:0]:
Length from HSYNC leading edge to first non-BLANK pixel
measured in number of pixels. Writing N indicates that the first non-BLANK pixel is
pixel number N+1. (e.g. - BHstart = 99, to have the first non-BLANK pixel on VCLK
number 100)
BVend[15:0]:
Length from VSYNC edge to last non-BLANK line measured in
number of lines. Writing N indicates that the last non-BLANK line is line N. (e.g. -
BVend = 241, to have the last non-BLANK line on line number 241)
BHend[9:0]:
Length from HSYNC leading edge to last non-BLANK pixel
measured in number of pixels. Writing N indicates that the last non-BLANK pixel is
pixel number N. (e.g. - BHend = 720, to have the last non-BLANK pixel on VCLK
number 720)
Active Area Registers
Address: 0x042 - 0x049
Parameters used to define the ‘a(chǎn)ctive area’ rectangle of the processed video.
Master/Slave modes do not affect these parameters.
Horizontal measures are in number of VCLKs (1 VCLK = 1 pixel, regardless of the
video bus width), from the leading edge of HSYNC.
Vertical measures are in number of HSYNCs (1 HSYNC = 1 line), from the leading
or trailing edge of VSYNC according to the FIVedge parameter.
Vstart[15:0]:
Length from VSYNC edge to first active (processed) line measured
in number of lines. Writing N indicates that the first active line is line N+1. (e.g. -
Vstart = 11, to have the first active line on line number 12).
Vend[15:0]:
Length from VSYNC edge to last active (processed) line measured in
number of lines. Writing N indicates that the last line is line N. (e.g. - Vend = 241,
to have the last line on line number 241).
Maximum permitted value for (Vend - Vstart) is 32768.
Hstart[9:0]:
Length from HSYNC leading edge to first active (processed) pixel
measured in number of pixels. Writing N indicates that the first active pixel is pixel
number N+1. (e.g. - Hstart = 99, to have the first active pixel on VCLK number 100).
Hend[9:0]:
Length from HSYNC leading edge to last active (processed) pixel
measured in number of pixels. Writing N indicates that the last active pixel is pixel
number N. (e.g. - Hend = 720, to have the last active pixel on VCLK number 720).
Maximum permitted value for (Hend - Hstart) is 768.
0x036
0x037
0x038
0x039
0x03A
0x03B
0x03C
0x03D
0x03E
0x03F
7
6
5
4
Vtotal [15:8]
Vtotal [7:0]
Htotal [9:8]
Htotal [7:0]
VsyncSize [7:0]
HsyncSize [7:0]
BVstart [7:0]
BHstart [7:0]
BVend [15:8]
BVend [7:0]
3
2
1
0
R/W
X
default
type
0x040
0x041
BHend [9:8]
BHend [7:0]
0x042
0x043
0x044
0x045
0x046
0x047
0x048
0x049
7
6
5
4
Vstart [15:8]
Vstart [7:0]
Vend [15:8]
Vend [7:0]
Hstart [9:8]
Hstart [7:0]
Hend [9:8]
Hend [7:0]
3
2
1
0
R/W
X
default
type
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZR36060 | Circular Connector; No. of Contacts:19; Series:; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:14; Circular Contact Gender:Socket; Circular Shell Style:Cable Receptacle; Insert Arrangement:14-19 |
| ZR36060PQC | Integrated JPEG CODEC |
| ZR36067 | AV PCI CONTROLLER |
| ZR36067PQC | AV PCI CONTROLLER |
| ZR36067 | PCI Adapter Intended for Multimedia Applications on PCI Systems(PCI（外圍部件互連）適配器（用于PCI系統(tǒng)的多媒體）) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZR36060PQC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Integrated JPEG CODEC |
| ZR36060PQC-27 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| ZR36060PQC-29.5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| ZR36067 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:AV PCI CONTROLLER |
| ZR36067PQC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:AV PCI CONTROLLER |
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