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參數(shù)資料
| 型號： | ZL30410 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | CONN HDR INVERSE 30POS 5ROW VERT |
| 中文描述： | 多業(yè)務線卡鎖相環(huán) |
| 文件頁數(shù)： | 10/38頁 |
| 文件大?。?/td> | 400K |
| 代理商： | ZL30410 |
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ZL30410
Data Sheet
10
Zarlink Semiconductor Inc.
Using RefAlign with 1.544 MHz, 2.048 MHz or 19.44 MHz Reference
If the ZL30410 is locked to a 1.544 MHz, 2.048 MHz or 19.44 MHz reference, then the output clocks can be brought
into phase alignment with the PLL reference by using the RefAlign control pin according to the following procedure:
-
Wait until the ZL30410 LOCK indication is high, indicating that it is locked
-
Pull RefAlign low
-
Hold RefAlign low for 250 μs
-
Pull RefAlign high
After initiating a reference realignment the PLL will enter Holdover mode for 200ns while aligning the internal clocks
to remove static phase error. The PLL will then begin the normal locking procedure.
Using RefAlign with an 8 kHz Reference
If the ZL30410 is locked to an 8 kHz reference, then the output clocks can be brought into phase alignment with the
PLL reference by using the RefAlign control pin according to the following procedure:
-
Wait until the ZL30410 LOCK indication is high, indicating that it is locked
-
Pull RefAlign low
-
Hold RefAlign low for 3 sec
-
Pull RefAlign high
After initiating a reference realignment the PLL will enter Holdover mode for 200ns while aligning the internal clocks
to remove static phase error. The PLL will then begin the normal locking procedure.
2.3 Clock Synthesizer
The output of the Core PLL is connected to the Clock Synthesizer that generates twelve clocks and three frame
pulses.
2.3.1 Output Clocks
The ZL30410 provides the following clocks (see Figure 15 "ST-BUS and GCI Output Timing", Figure 16 "DS1 and
DS2 Clock Timing", Figure 17 "C155o and C19o Timing", and Figure 20 "E3 and DS3 Output Timing" for details):
- C1.5o
: 1.544 MHz clock with nominal 50% duty cycle
- C2o
: 2.048 MHz clock with nominal 50% duty cycle
- C4o
: 4.096 MHz clock with nominal 50% duty cycle
- C6o
: 6.312 MHz clock with nominal 50% duty cycle
- C8o
: 8.192 MHz clock with nominal 50% duty cycle
- C8.5o
: 8.592 MHz clock with duty cycle from 30 to 70%.
- C11o
: 11.184 MHz clock with duty cycle from 30 to 70%.
- C16o
: 16.384 MHz clock with nominal 50% duty cycle
- C19o
: 19.44 MHz clock with nominal 50% duty cycle
- C34o
: 34.368 MHz clock with nominal 50% duty cycle
- C44o
: 44.736 MHz clock with nominal 50% duty cycle
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| ZL30410QCC | CONN SOCKET R/A 4R0W 24POS SLD |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL30410_06 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-service Line Card PLL |
| ZL30410QCC | 制造商:Microsemi Corporation 功能描述:PLL CLOCK GEN SGL UP TO 19.44MHZ 80LQFP EP - Trays |
| ZL30410QCC1 | 制造商:Microsemi Corporation 功能描述: |
| ZL30410QCG1 | 制造商:Microsemi Corporation 功能描述:IC SONET/SDH NETWORK ELEMENT PLL 制造商:Microsemi Corporation 功能描述:LEAD FREE SONET/SDH NETWORK ELEMENT PLL - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC PLL SONET/SDH/PDH 80LQFP 制造商:Microsemi Corporation 功能描述:IC PLL SONET/SDH/PDH 80LQFP |
| ZL30414 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH Clock Multiplier PLL |
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