![](http://datasheet.mmic.net.cn/Exar-Corporation/XRT94L33IB-L_datasheet_100163/XRT94L33IB-L_342.png)
XRT94L33
xr
Rev.1.2.0.
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
342
2.3.1.3.3
The In-Frame State
Once the Receive STS-3 TOH Processor block reaches this state, it is considered to be operating in a
“Normal” manner. In this mode, the Receive STS-3 TOH Processor block will continue to monitor and check
the value of the Framing Alignment bytes within the incoming STS-3 data-stream.
In general, the Receive STS-3 TOH Processor block will be tolerant to some occasional Framing Byte errors.
However, if the Receive STS-3 TOH Processor block were to detect framing alignment bit errors in four
consecutive SONET frames (within the incoming STS-3 data-stream), then it will declare the “SEF” defect. As
the Receive STS-3 TOH Processor declares the SEF defect, then it will transition into the “SEF = 1, LOF = 0”
state.
As the Receive STS-3 TOH Processor block transitions from the “In-Frame” to the “SEF = 1, LOF = 0” state, it
will do all of the following.
5.
It will set Bit 1 (SEF Defect Declared) within the “Receive STS-3 Transport Status Register – Byte 0”
to “1”, as depicted below.
Receive STS-3 Transport Status Register – Byte 0 (Address = 0x1107)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RDI-L
Defect
Declared
S1 Byte
Unstable
Defect
Declared
K1, K2 Byte
Unstable
Defect
Declared
SF Defect
Declared
SD Defect
Declared
LOF
Defect
Declared
SEF
Defect
Declared
LOS
Defect
Declared
R/O
0
1
0
6.
It will generate the “Change of SEF Defect Condition” interrupt. The XRT94L33 will indicate that it is
generating this interrupt by doing the following.
a.
Toggling the “INT*” input pin “l(fā)ow” and
b.
Setting Bit 1 (Change of SEF Defect Condition Interrupt Status), within the “Receive STS-3 Transport
Interrupt Status Register – Byte 0” as depicted below.
Receive STS-3 Transport Interrupt Status Register – Byte 0 (Address = 0x110B)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Change of
SF Defect
Condition
Interrupt
Status
Change of
SD Defect
Condition
Interrupt
Status
Detection of
REI-L Error
Interrupt
Status
Detection of
B2 Byte
Error
Interrupt
Status
Detection of
B1 Byte
Error
Interrupt
Status
Change of
LOF Defect
Condition
Interrupt
Status
Change of
SEF Defect
Condition
Interrupt
Status
Change of
LOS Defect
Condition
Interrupt
Status
RUR
0
1
0
2.3.1.3.4
The SEF = 1, LOF = 0 State
Once the Receive STS-3 TOH Processor block reaches this state, then it has already declared the “SEF
Defect Condition”. For the duration that the Receive STS-3 TOH Processor block is operating in the “SEF =
1, LOF = 0” state, the Receive STS-3 TOH Processor block will be testing the Framing Alignment bytes (A1
and A2) within the incoming STS-3 signal, in order to determine if it should declare the “LOF” or the “In-
Frame” condition.