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XRT94L33
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Rev.1.2.0.
331
2.2.9.5.14
SCRAMBLING DATA
The Transmit STS-3 TOH Processor block permits the user to either enable or disable scrambling of the STS-
3 data, prior to it being transmitted to the remote terminal equipment. The customer can accomplish this by
writing the appropriate value into Bit 2 (Scramble Enable), within the Transmit STS-3 Transport – SONET
Transmit Control Register, as depicted below.
Transmit STS-3 Transport – SONET Transmit Control Register – Byte 0 (Address = 0x1902)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
M0M1 Insert
Method[0]
Unused
RDI-L Force
AIS-L Force
LOS Force
Scramble
Enable
B2 Error
Insert
A1A2 Error
Insert
R/W
R/O
R/W
0
X
0
Setting this bit-field to “1” enables the Scrambler.
Conversely, setting this bit-field to “0” disables the
Scrambler.
If the Scrambler is enabled, then it will scramble the “outbound” STS-3 data with a generating polynomial of x
7
+ x
6 + 1 and a sequence length of 127.
2.3
RECEIVE DIRECTION
If a given channel (or the entire device) is configured to operate in the ATM Mode, then the purpose of the
Receive Section within the XRT94L33 1-Channel STS-3c/STS-3 ATM UNI device is to permit a local ATM
Layer (or ATM Adaptation Layer) processor to receive ATM cell data from a remote piece of equipment via an
STS-3, STS-3c or DS3/E3 transport medium.
For ATM UNI Applications, the Receive Section of the XRT94L33 chip consists of the following blocks.
Receive STS-3 TOH Processor Block
Receive STS-3c POH Processor Block (for STS-3c Applications)
Receive SONET POH Processor Block (for STS-3 Applications)
Receive ATM Cell Processor Block
Receive UTOPIA Interface Block
The Receive STS-3 TOH Processor block will receive an STS-3 signal, either over the PECL interface or via
the Receive STS-3 Telecom Bus Interface. As the Receive STS-3 TOH Processor block receives this signal,
it will do the following.
It will locate the boundaries of the incoming STS-3 frames
It will compute and verify the B1 and B2 bytes
It will detect and clear the LOS, SEF, LOF, RDI-L and AIS-L defect condition
It will detect and flag REI-L events
It will detect and clear the SD and SF conditions
It will route the STS-3c SPE data to the Receive STS-3c POH Processor block for further processing.
The Receive STS-3c POH Processor block will receive the STS-3c SPE data from the Receive STS-3 TOH
Processor block. As the Receive STS-3c POH Processor block receives this signal, it will do the following.
It will compute and verify the B3 bytes
It will detect and clear the LOP-P, RDI-P and AIS-P defect conditions