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參數(shù)資料
| 型號： | XRT91L82IB |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
| 中文描述： | TRANSCEIVER, PBGA196 |
| 封裝： | 15 X 15 MM, STBGA-196 |
| 文件頁數(shù)： | 7/59頁 |
| 文件大?。?/td> | 414K |
| 代理商： | XRT91L82IB |
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xr
REV. P1.0.5
PRELIMINARY
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L82
4
PIN DESCRIPTIONS
COMMON CONTROL
N
AME
L
EVEL
T
YPE
P
IN
D
ESCRIPTION
RESET
LVTTL,
LVCMOS
I
E5
Master Reset Input
Active low signal. When this pin is pulled "Low" for more than
30ns, the internal registers are set to their default state. See
the register description for the default values.
This pin is provided with an internal pull-up.
PIO_CFG1
PIO_CFG0
LVTTL,
LVCMOS
I
D3
E3
Parallel I/O Configuration
Selects parallel I/O to be differential LVDS, differential
LVPECL, or Single-Ended LVPECL based on table below.
This pin is provided with an internal pull-down.
XRES1P
XRES1N
-
I
E14
F14
External LVDS Biasing Resistors
A 402
resistor with +/-1% tolerance should be placed across
these 2 pins for proper biasing. Although unecessary in
LVPECL operation, this resistor is required in LVDS operation.
See Figure 8 on page 22.
SE_REF
Analog
O
L7
Single-Ended LVPECL Biasing Output Reference
VBB
100K output bias reference.
Maximum load capacitance is 30pF. Maximum sourcing/sinking
capability is 750
μ
A and 1000
μ
A respectively.
SEREFDIS
LVTTL,
LVCMOS
I
C3
SE_REF Power down Control
Powers down SE_REF and reduces power consumption.
"Low" = SE_REF Enabled
"High" = SE_REF Disabled
This pin is provided with an internal pull-up.
REF1CLKP
REF1CLKN
LVPECL Diff
I
A13
B13
Reference Clock Input 1
This differential clock input reference is used for the transmit
clock multiplier unit (CMU) and clock data recovery (CDR) to
provide the necessary high-speed clock reference for this
device. Pin REFREQSEL[1:0] determines the value used as
the reference. See Pin REFREQSEL[1:0] for more details.
Internally terminated and biased.
PIO_CFG
[1:0]
VDD_I/O
Input
Configuration
Output
Configuration
00
3.3V
3.3V
Differential
LVPECL
3.3V
Differential
LVPECL
01
3.3V
3.3V
Single-Ended
LVPECL
3.3V
Single-Ended
LVPECL
10
3.3V
3.3V
Differential LVDS
3.3V
Differential LVDS
11
Reserved
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PDF描述 |
|---|---|
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| XRT94L31 | 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER |
| XRT94L31IB | 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER |
| XRT94L43A | SONET/SDH OC-12 TO 12XDS3/E3 MAPPER |
| XRT94L43 | SONET/SDH STS-12/STM-4 TO E3/DS3/STS-1 MAPPER/DEMAPPER |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XRT91L82IB-F | 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| XRT94L31 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC |
| XRT94L31_07 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC |
| XRT94L31ES-L04 | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRT94L31IB | 功能描述:網絡控制器與處理器 IC Demapper RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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