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參數(shù)資料
| 型號： | XRT91L82IB |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
| 中文描述： | TRANSCEIVER, PBGA196 |
| 封裝： | 15 X 15 MM, STBGA-196 |
| 文件頁數(shù)： | 27/59頁 |
| 文件大?。?/td> | 414K |
| 代理商： | XRT91L82IB |
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xr
REV. P1.0.5
PRELIMINARY
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L82
24
3.2
When applying parallel data input to the transmitter, the setup and hold times should be followed as shown in
Figure 11 and Table 8. Table 9 shows the parameters for TXPCLKOP/N clock output.
F
IGURE
11. T
RANSMIT
P
ARALLEL
I
NPUT
T
IMING
Transmit Parallel Data Input Timing
T
ABLE
8: T
RANSMIT
P
ARALLEL
D
ATA
AND
C
LOCK
I
NPUT
T
IMING
S
PECIFICATION
T
ABLE
9: T
RANSMIT
P
ARALLEL
C
LOCK
O
UTPUT
T
IMING
S
PECIFICATION
3.3
The Parallel Interface also includes a 16x9 FIFO that can be used to eliminate difficult timing issues between
the input transmit clock and the clock derived from the CMU. The use of the FIFO permits the system to
tolerate an arbitrary amount of delay and jitter between TXPCLKOP/N and TXPCLKIP/N. The FIFO can be
initialized when FIFO_RST is asserted and held "High" for 2 cycles of the TXPCLKOP/N clock. When the
FIFO_RST is de-asserted, it will take 8 to 10 TXPCLKOP/N cycles for the FIFO to flush out. Once the FIFO is
centered, the delay between TXPCLKOP/N and TXPCLKIP/N can decrease or increase up to two periods of
the low-speed clock. Should the delay exceed this amount, the read and write pointers will point to the same
word in the FIFO resulting in a loss of transmitted data (FIFO overflow). In the event of a FIFO overflow, the
FIFO control logic will initiate an OVERFLOW signal that can be used by an external controller to issue a FIFO
RESET signal.
Transmit FIFO
S
YMBOL
P
ARAMETER
M
IN
T
YP
M
AX
U
NITS
t
TXPCLKI
Transmit parallel clock input period (155.52 MHz non-FEC rate)
6.43
ns
t
TXPCLKI
Transmit parallel clock input period (166.63 MHz FEC rate)
6.00
ns
t
TXDI_SU
TXPCLKIP/N "High" to data setup time
1000
ps
t
TXDI_HD
TXPCLKIP/N "High" to data hold time
500
ps
TX
DUTY
TXPCLKIP/N Duty Cycle
40
60
%
S
YMBOL
P
ARAMETER
M
IN
T
YP
M
AX
U
NITS
t
TXPCLKO
Transmit parallel clock output period (155.52 MHz non-FEC rate)
6.43
ns
t
TXPCLKO
Transmit parallel clock output period (166.63 MHz FEC rate)
6.00
ns
TX
DUTY
TXPCLKOP/N Duty Cycle
45
55
%
TXPCLKIP/N
TXDI[15:0]P/N
t
TXDI_SU
t
TXDI_HD
t
TXPCLKI
t
TXPCLKO
TXPCLKOP/N
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相關(guān)代理商/技術(shù)參數(shù) |
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| XRT91L82IB-F | 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| XRT94L31 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC |
| XRT94L31_07 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC |
| XRT94L31ES-L04 | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRT94L31IB | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Demapper RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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