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參數(shù)資料
| 型號： | XRT91L82IB |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
| 中文描述： | TRANSCEIVER, PBGA196 |
| 封裝： | 15 X 15 MM, STBGA-196 |
| 文件頁數(shù)： | 33/59頁 |
| 文件大?。?/td> | 414K |
| 代理商： | XRT91L82IB |
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xr
REV. P1.0.5
PRELIMINARY
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L82
30
4.0
DIAGNOSTIC FEATURES
4.1
RLOOPS_PRBSCLR is a dual function pin that serves as both serial remote loopback enable and PRBS error
clear function. The serial remote loopback function is activated by setting RLOOPS_PRBSCLR "Low". When
serial remote loopback is activated, the high-speed serial receive data from RXIP/N is presented at the high-
speed transmit output TXOP/N, and the high-speed recovered clock is selected and presented to the high-
speed transmit clock output TXSCLKOP/N. During serial remote loopback, the high-speed receive data (RXIP/
N) is also converted to parallel data and presented at the low-speed receive parallel interface RXDO[15:0]P/N.
The recovered receive clock is also divided by 16 and presented at the low-speed clock output RXPCLKOP/N
to synchronize the transfer of the 16-bit received parallel data. In PRBS Test Mode, serial remote loopback is
not available when the PRBS generator and analyzer is enabled. This pin serve as the PRBS error clear
(PRBSCLR) function to reset the PRBS_ERR error output indicator. A simplified block diagram of serial
remote loopback is shown in Figure 18.
Serial Remote Loopback
4.2
RLOOPP controls a more comprehensive version of remote loopback that can also be used in conjunction with
the de-jitter PLL that is phase locked to the recovered receive clock. In this mode, the received signal is
processed by the CDR, and is sent through the serial to parallel converter. At this point, the 16-bit parallel data
and clock are looped back to the transmit FIFO. Concurrently, if receive clock jitter attenuation is also
employed, the received clock is divided down in frequency and presented to the input of the integrated phase/
frequency detector and is compared to the frequency of a VCXO that is connected to the VCXO_IN input. With
the LOOPTM_JA configured to use the recovered receive clock as the reference and VCXO_SEL asserted,
the VCXO is phase locked to the recovered receive clock. The de-jittered clock is then used to retime the
transmitter, resulting in the re-transmission of the de-jittered received data out of TXOP/N. A FIFO reset using
FIFO_RST should follow immediately after enabling/disabling parallel remote loopback. A simplified block
diagram of parallel remote loopback is shown in Figure 19.
Parallel Remote Loopback (Host Mode Only)
F
IGURE
18. S
ERIAL
R
EMOTE
L
OOPBACK
F
IGURE
19. P
ARALLEL
R
EMOTE
L
OOPBACK
PISO
Re-Timer
CML
Output Drivers
FIFO
SIPO
CDR
CML
Input Drivers
Serial Remote Loopback
RX Parallel Output
TX Serial Output
RX Serial Input
PISO
Re-Timer
CML
Output Drivers
FIFO
SIPO
CDR
CML
Input MUX
Parallel Remote Loopback
RX Parallel Output
TX Serial Output
RX Serial Input
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| XRT91L82IB-F | 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| XRT94L31 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC |
| XRT94L31_07 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC |
| XRT94L31ES-L04 | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRT94L31IB | 功能描述:網(wǎng)絡控制器與處理器 IC Demapper RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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