參數(shù)資料
型號: XRT91L82IB
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
中文描述: TRANSCEIVER, PBGA196
封裝: 15 X 15 MM, STBGA-196
文件頁數(shù): 14/59頁
文件大?。?/td> 414K
代理商: XRT91L82IB
XRT91L82
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
PRELIMINARY
xr
REV. P1.0.5
11
RECEIVER SECTION
N
AME
L
EVEL
T
YPE
P
IN
D
ESCRIPTION
RXDO0P
RXDO0N
RXDO1P
RXDO1N
RXDO2P
RXDO2N
RXDO3P
RXDO3N
RXDO4P
RXDO4N
RXDO5P
RXDO5N
RXDO6P
RXDO6N
RXDO7P
RXDO7N
RXDO8P
RXDO8N
RXDO9P
RXDO9N
RXDO10P
RXDO10N
RXDO11P
RXDO11N
RXDO12P
RXDO12N
RXDO13P
RXDO13N
RXDO14P
RXDO14N
RXDO15P
RXDO15N
LVDS,
LVPECL
Diff and SE
O
G5
G4
H4
H3
H7
H6
H8
J8
J3
J2
J6
J5
K2
K1
K5
K4
K8
K7
L3
L2
L6
L5
L8
M8
M2
M1
M5
M4
M7
N7
N6
N5
Receive Parallel Data Output
155.52 Mbps 16-bit parallel receive data output is updated
simultaneously on the falling edge of the RXPCLKOP/N output.
The 16-bit parallel interface is de-multiplexed from the receive
serial data input, MSB first (RXDO15P/N). For LVPECL Single-
Ended applications, all the negative polarity "N" pins should not
be connected.
N
OTE
:
The XRT91L82 can output 166.63 Mbps 16-bit parallel
receive data output for Forward Error Correction (FEC)
Applications.
RXIP
RXIN
CMLDIFF
I
A2
A3
Receive Serial Data Input
The receive serial data stream of 2.488 Gbps is applied to
these input pins. In Forward Error Correction, the receive
serial data stream is 2.666 Gbps. This pin is internally biased
and terminated.
RXPCLKOP
RXPCLKON
LVDS,
LVPECL
Diff and SE
O
P5
P4
Receive Parallel Clock Output
155.52 MHz parallel clock output used to update the 16-bit par-
allel receive data output RXDO[15:0]P/N at the falling edge of
this clock.
N
OTE
:
The XRT91L82 can output a 166.63 MHz receive clock
output for Forward Error Correction (FEC).
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