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參數(shù)資料
| 型號： | XRT91L82IB |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
| 中文描述： | TRANSCEIVER, PBGA196 |
| 封裝： | 15 X 15 MM, STBGA-196 |
| 文件頁數(shù)： | 22/59頁 |
| 文件大?。?/td> | 414K |
| 代理商： | XRT91L82IB |
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XRT91L82
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
PRELIMINARY
xr
REV. P1.0.5
19
2.2
These external loop filter 0
resistors and 22
μ
F non-polarized capacitor provide the necessary components to
achieve the required receiver jitter performance. They must be well isolated to prohibit noise entering the CDR
block. Figure 5 shows the pin connections and external loop filter components. The external loop filter is not
needed while in host mode and RXCAP1N becomes the charge pump output for the external VCXO.
External Receive Loop Filter Capacitors
2.3
The clock and data recovery unit accepts the high-speed NRZ serial data from the differential CML receiver
and generates a clock that is the same frequency as the incoming data. The clock recovery utilizes
REF1CLKP/N and/or REF2CLKP/N to train and monitor its clock recovery PLL. Initially upon startup, the PLL
locks to the local reference clock within ±500 ppm. Once this is achieved, the PLL then attempts to lock onto
the incoming receive data stream. Whenever the recovered clock frequency deviates from the local reference
clock frequency by more than approximately ±500 ppm, the clock recovery PLL will switch and lock back onto
the local reference clock. When this condition occurs the PLL will declare Loss of Lock and the
LOCKDET_CDR signal will be pulled "Low." Whenever a Loss of Lock/Loss of Signal Detection (LOSD) event
occurs, the CDR will continue to supply a receive clock (based on the local reference clock) to the upstream
framer device. A Loss of Lock condition will also be declared when the external SDEXT becomes inactive.
When the SDEXT is de-asserted by the optical module or when DISRD is asynchronously asserted "Low,"
receive parallel data output will be forced to a logic zero state for the entire duration that a LOSD condition is
detected or for as long as DISRD is asserted "Low." This acts as a receive data mute upon LOSD function to
prevent random noise from being misinterpreted as valid incoming data. When the SDEXT becomes active
and the recovered clock is determined to be within ±500 ppm accuracy with respect to the local reference
source, the clock recovery PLL will switch and lock back onto the incoming receive data stream and the lock
detect output (LOCKDET_CDR) will go active. Table 5 specifies the Clock and Data Recovery Unit
performance characteristics.
Receive Clock and Data Recovery
F
IGURE
5. E
XTERNAL
L
OOP
F
ILTER
RXCAP1N
CP_OUT (HOST)
RXCAP1P
0
0
22uF
non-polarized
pin E1
pin F1
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| XRT91L82IB-F | 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| XRT94L31 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC |
| XRT94L31_07 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC |
| XRT94L31ES-L04 | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRT94L31IB | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Demapper RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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