參數(shù)資料
型號: XRT91L82IB
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
中文描述: TRANSCEIVER, PBGA196
封裝: 15 X 15 MM, STBGA-196
文件頁數(shù): 45/59頁
文件大?。?/td> 414K
代理商: XRT91L82IB
xr
REV. P1.0.5
PRELIMINARY
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L82
42
T
ABLE
18: M
ICROPROCESSOR
R
EGISTER
0
X
04
H
B
IT
D
ESCRIPTION
O
UTPUT
C
ONTROL
R
EGISTER
(0
X
04
H
)
B
IT
N
AME
F
UNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved
This Register Bit is Not Used
X
X
D6
Reserved
This Register Bit is Not Used
X
X
D5
Reserved
This Register Bit is Not Used
X
X
D4
Reserved
This Register Bit is Not Used
X
X
D3
DISRD
Receive Parallel Data Output Disable
If this bit is set to "0", the 16-bit parallel receive data output will
asynchronously mute.
"0" = Forces RXDO[15:0]P/N to a logic state "0"
"1" = Normal Mode
R/W
1
D2
DISRDCLK
Receive Parallel Clock Output Disable
This bit is used to asynchronously control the activity of the parallel
receive clock output.
"0" = Forces RXPCLKOP/N to a logic state of "0"
"1" = Normal Mode
R/W
1
D1
TXSCLKOOFF
Transmit Serial Clock Output Tristate
This bit is used to control the activity of the 2.488/2.666 GHz
differential serial clock output. Tristating TXSCLKOP/N output
reduces power consumption.
"0" = TXSCLKOP/N output Enabled
"1" = TXSCLKOP/N output Tristated
R/W
1
D0
CDRLCKREF
CDR’s Recovered High-speed Serial Clock Reference
Controls CDR’s operation.
"0" = Forced to lock to CDR PLL reference training clock
"1" = Normal Operation (Locked to incoming serial data)
R/W
1
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