參數(shù)資料
型號： XRT91L82IB
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
中文描述： TRANSCEIVER, PBGA196
封裝： 15 X 15 MM, STBGA-196
文件頁數(shù)： 13/59頁
文件大小： 414K
代理商： XRT91L82IB
xr
REV. P1.0.5
PRELIMINARY
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L82
10
TXCLKO16P
TXCLKO16N
LVDS,
LVPECL
Diff and SE
O
P2
P1
Auxiliary Clock Output (155.52/19.44 MHz)
155.52 or 19.44 MHz auxiliary clock derived from CMU output.
This clock can also be used for the downstream device as a ref-
erence for generating the TXDI[15:0]P/N data and TXPCLKIP/
N clock input. This enables the downstream device and the
STS-48 transceiver to be in synchronization. The frequency
output of this pin is controlled by TXCLKO16SEL.
N
OTE
:
This pin can output a 166.63/20.83 MHz transmit clock
output for Forward Error Correction (FEC).
TXCLKO16SEL
LVTTL,
LVCMOS
I
C4
Auxiliary Clock Output Select
This pin is used to select the auxiliary clock output.
"Low" = TXCLKO16P/N outputs 155.52/ 166.63 MHz
"High" = TXCLKO16P/N outputs 19.44/ 20.83 MHz
This pin is provided with an internal pull-down.
LOCKDET_CMU
LVCMOS
O
C6
CMU Lock Detect
This pin is used to monitor the lock condition of the clock multi-
plier unit.
"Low" = CMU Out of Lock
"High" = CMU Locked
OVERFLOW
LVCMOS
O
D6
Transmit FIFO Overflow
This pin is used to monitor the transmit FIFO status.
"Low" = Normal Status
"High" = Overflow Condition
FIFO_RST
LVTTL,
LVCMOS
I
D5
FIFO Control Reset
FIFO_RST should be held "High" for a minimum of 2 TXP-
CLKOP/N cycles after powering up and during manual FIFO
reset. After the FIFO_RST pin is returned "Low," it will take 8 to
10 TXPCLKOP/N cycles for the FIFO to flush out. Upon an
interrupt indication that the FIFO has an overflow condition, this
pin is used to reset or flush out the FIFO.
"Low" = Normal Operation
"High" = Manual FIFO Reset
This pin is provided with an internal pull-down.
N
OTES
:
1.
In Hardware Mode
, to automatically reset the FIFO, tie the
OVERFLOW output pin to the FIFO_RST input pin or if
desired, an asynchronous FIFO reset pin and the OVER-
FLOW output pin can be logically ’OR’ed and the output
tied to the FIFO_RST input pin.
2.
In Host Mode
, this pin is disabled and not used.
FIFO_RST is asserted through Microprocessor Control
Register 0x03
H
Bit-D0. A FIFO_AUTORST bit is also
available on Microprocessor Control Register 0x03
H
Bit-
D1.
TRANSMITTER SECTION
N
AME
L
EVEL
T
YPE
P
IN
D
ESCRIPTION
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT91L82IB-F 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
XRT94L31 制造商:EXAR 制造商全稱:EXAR 功能描述:3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
XRT94L31_07 制造商:EXAR 制造商全稱:EXAR 功能描述:3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
XRT94L31ES-L04 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT94L31IB 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Demapper RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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