
XRT86VL38
151
OCTAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
REV. V1.2.0
TABLE 130: LIU GLOBAL CONTROL REGISTER 5 (LIUGCR5)
HEX ADDRESS: 0X0FEA
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
GCHIS7
RUR/
WC
0
Global Channel 7 Interrupt Status Indicator
This Reset-Upon-Read bit field indicates whether or not an interrupt
has occurred on Channel 7 within the XRT86VL38 device since the
last read of this register.
0 = Indicates that No interrupt has occurred on Channel 7 within the
XRT86VL38 device since the last read of this register.
1 = Indicates that an interrupt has occurred on Channel 7 within the
XRT86VL38 device since the last read of this register.
6
GCHIS6
RUR/
WC
0
Global Channel 6 Interrupt Status Indicator
This Reset-Upon-Read bit field indicates whether or not an interrupt
has occurred on Channel 6 within the XRT86VL38 device since the
last read of this register.
0 = Indicates that No interrupt has occurred on Channel 6 within the
XRT86VL38 device since the last read of this register.
1 = Indicates that an interrupt has occurred on Channel 6 within the
XRT86VL38 device since the last read of this register.
5
GCHIS5
RUR/
WC
0
Global Channel 5 Interrupt Status Indicator
This Reset-Upon-Read bit field indicates whether or not an interrupt
has occurred on Channel 5 within the XRT86VL38 device since the
last read of this register.
0 = Indicates that No interrupt has occurred on Channel 5 within the
XRT86VL38 device since the last read of this register.
1 = Indicates that an interrupt has occurred on Channel 5 within the
XRT86VL38 device since the last read of this register.
4
GCHIS4
RUR/
WC
0
Global Channel 4 Interrupt Status Indicator
This Reset-Upon-Read bit field indicates whether or not an interrupt
has occurred on Channel 4 within the XRT86VL38 device since the
last read of this register.
0 = Indicates that No interrupt has occurred on Channel 4 within the
XRT86VL38 device since the last read of this register.
1 = Indicates that an interrupt has occurred on Channel 4 within the
XRT86VL38 device since the last read of this register.
3
GCHIS3
RUR/
WC
0
Global Channel 3 Interrupt Status Indicator
This Reset-Upon-Read bit field indicates whether or not an interrupt
has occurred on Channel 3 within the XRT86VL38 device since the
last read of this register.
0 = Indicates that No interrupt has occurred on Channel 3 within the
XRT86VL38 device since the last read of this register.
1 = Indicates that an interrupt has occurred on Channel 3 within the
XRT86VL38 device since the last read of this register.