TABLE
參數(shù)資料
型號: XRT86VL38IB-F
廠商: Exar Corporation
文件頁數(shù): 152/160頁
文件大?。?/td> 0K
描述: IC LIU/FRAMER T1/E1/J1 8CH 420BG
標(biāo)準(zhǔn)包裝: 40
控制器類型: T1/E1/J1 調(diào)幀器,LIU
電源電壓: 3.3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 420-BBGA
供應(yīng)商設(shè)備封裝: 420-PBGA
包裝: 托盤
其它名稱: 1016-1487
XRT86VL38IB-F-ND
XRT86VL38
86
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 67: PMON RECEIVE CRC-6 BIT ERROR COUNTER - MSB (RSBBECU)
HEX ADDRESS: 0Xn905
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
RSBBEC[15]
RUR
0
Performance Monitor “Receive Synchronization Bit Error 16-Bit
Counter” - Upper Byte:
These RESET-upon-READ bits, along with that within the “PMON
Receive Synchronization Bit Error Counter Register LSB” combine
to reflect the cumulative number of instances that the Receive Syn-
chronization Bit errors has been detected by the Receive T1 Framer
block since the last read of this register.
This register contains the Most Significant byte of this 16-bit of the
Receive Synchronization Bit Error counter.
NOTE: For all 16-bit wide PMON registers, user must read the MSB
counter first before reading the LSB counter in order to read
the accurate PMON counts. To clear PMON count, user
must read the MSB counter first before reading the LSB
counter in order to clear the PMON count.
6
RSBBEC[14]
RUR
0
5
RSBBEC[13]
RUR
0
4
RSBBEC[12]
RUR
0
3
RSBBEC[11]
RUR
0
2
RSBBEC[10]
RUR
0
1
RSBBEC[9]
RUR
0
RSBBEC[8]
RUR
0
TABLE 68: PMON RECEIVE CRC-6 BIT ERROR COUNTER - LSB (RSBBECL)
HEX ADDRESS: 0Xn906
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
RSBBEC[7]
RUR
0
Performance Monitor “Receive Synchronization Bit Error 16-Bit
Counter” - Lower Byte:
These RESET-upon-READ bits, along with that within the “PMON
Receive Synchronization Bit Error Counter Register MSB” combine
to reflect the cumulative number of instances that the Receive Syn-
chronization Bit errors has been detected by the Receive T1 Framer
block since the last read of this register.
This register contains the Least Significant byte of this 16-bit of the
Receive Synchronization Bit Error counter.
NOTE: For all 16-bit wide PMON registers, user must read the MSB
counter first before reading the LSB counter in order to read
the accurate PMON counts. To clear PMON count, user
must read the MSB counter first before reading the LSB
counter in order to clear the PMON count.
6
RSBBEC[6]
RUR
0
5
RSBBEC[5]
RUR
0
4
RSBBEC[4]
RUR
0
3
RSBBEC[3]
RUR
0
2
RSBBEC[2]
RUR
0
1
RSBBEC[1]
RUR
0
RSBBEC[0]
RUR
0
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