TABLE
參數(shù)資料
型號(hào)： XRT86VL38IB-F
廠商： Exar Corporation
文件頁數(shù)： 53/160頁
文件大?。?/td> 0K
描述： IC LIU/FRAMER T1/E1/J1 8CH 420BG
標(biāo)準(zhǔn)包裝： 40
控制器類型： T1/E1/J1 調(diào)幀器，LIU
電源電壓： 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 420-BBGA
供應(yīng)商設(shè)備封裝： 420-PBGA
包裝： 托盤
其它名稱： 1016-1487
XRT86VL38IB-F-ND
XRT86VL38
141
OCTAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
REV. V1.2.0
TABLE 115: LIU CHANNEL CONTROL INTERRUPT STATUS REGISTER (LIUCCISR)
HEX ADDRESS: 0X0FN6
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
Reserved
RO
0
6
DMOIS_n
RUR/
WC
0
Change of Transmit DMO (Drive Monitor Output) Condition
Interrupt Status:
This RESET-upon-READ bit indicates whether or not the “Change of
the Transmit DMO Condition” Interrupt has occurred since the last
read of this register.
0 = Indicates that the “Change of the Transmit DMO Condition”
Interrupt has NOT occurred since the last read of this register.
1 = Indicates that the “Change of the Transmit DMO Condition”
Interrupt has occurred since the last read of this register.
This bit is set to a “1” every time when DMO_n status bit (bit 6
of Register 0x0Fn5) has changed since the last read of this
register.
NOTE: Users can determine the current state of the “Transmit DMO
Condition” by reading out the content of bit 6 within Register
0x0Fn5
5
FLSIS_n
RUR/
WC
0
FIFO Limit Interrupt Status:
This RESET-upon-READ bit indicates whether or not the “FIFO
Limit” Interrupt has occurred since the last read of this register.
0 = Indicates that the “FIFO Limit Status” Interrupt has NOT
occurred since the last read of this register.
1 = Indicates that the “FIFO Limit Status” Interrupt has occurred
since the last read of this register.
This bit is set to a “1” every time when FIFO Limit Status bit
(bit 5 of Register 0x0Fn5) has changed since the last read of
this register.
NOTE: Users can determine the current state of the “FIFO Limit” by
reading out the content of bit 5 within Register 0x0Fn5
4
Reserved
-
This bit is not used
3
NLCDIS_n
RUR/
WC
0
Change in Network Loop-Code Detection Interrupt Status:
This RESET-upon-READ bit indicates whether or not the “Change in
Network Loop-Code Detection” Interrupt has occurred since the last
read of this register.
0 = Indicates that the “Change in Network Loop-Code Detection”
Interrupt has NOT occurred since the last read of this register.
1 = Indicates that the “Change in Network Loop-Code Detection”
Interrupt has occurred since the last read of this register.
This bit is set to a “1” every time when NLCD status bit (bit 3 of Reg-
ister 0x0Fn5) has changed since the last read of this register.
NOTE: Users can determine the current state of the “Network Loop-
Code Detection” by reading out the content of bit 3 within
Register 0x0Fn5
2
Reserved
-
This bit is not used
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT86VL38IB-F 制造商:Exar Corporation 功能描述:T1/E1 Framer Combo IC
XRT86VL3X 制造商:EXAR 制造商全稱:EXAR 功能描述:T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
XRT86VL3X_07 制造商:EXAR 制造商全稱:EXAR 功能描述:T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
XRT86VL3X_0710 制造商:EXAR 制造商全稱:EXAR 功能描述:T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
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