參數(shù)資料
型號: XRT86VL38IB-F
廠商: Exar Corporation
文件頁數(shù): 108/160頁
文件大小: 0K
描述: IC LIU/FRAMER T1/E1/J1 8CH 420BG
標(biāo)準(zhǔn)包裝: 40
控制器類型: T1/E1/J1 調(diào)幀器,LIU
電源電壓: 3.3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 420-BBGA
供應(yīng)商設(shè)備封裝: 420-PBGA
包裝: 托盤
其它名稱: 1016-1487
XRT86VL38IB-F-ND
XRT86VL38
46
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
4
TxFr1544
R/W
0
Fractional/Signaling Interface Enabled
This bit is used to enable or disable the transmit fractional data interface, sig-
naling input, as well as the 32MHz transmit clock and the transmit overhead
Signal output.
0 = Configures the 5 time slot identifier pins (TxChn[4:0]) to output the channel
number as usual.
1 = Configures the 5 time slot identifier pins (TxChn[4:0]) to function as the fol-
lowing:
TxChn[0] becomes the Transmit Serial SIgnaling pin (TxSIG_n) for signaling
inputs. Signaling data can now be input from the TxSIG pin if configured
appropriately.
TxChn[1] becomes the Transmit Fractional Data Input pin (TxFrTD_n) for frac-
tional data input. Fractional data can now be input from the TxFrTD pin if con-
figured appropriately.
TxChn[2] becomes the 32 MHz transmit clock output
TxChn[3] becomes the Transmit Overhead Signal which pulses high on the
first bit of each multi-frame.
NOTE:
This bit has no effect in the high speed or multiplexed modes of
operation. In high-speed or multiplexed modes, TxCHN[0] functions
as TxSIGn for signaling input.
3
TxICLKINV
R/W
0
Transmit Clock Inversion (Backplane Interface)
This bit selects whether data transition will happen on the rising or falling edge
of the transmit clock.
0 = Selects data transition to happen on the rising edge of the transmit clocks.
1 = Selects data transition to happen on the falling edge of the transmit clocks.
NOTE:
This feature is only available for base rate configuration (i.e. non-
highspeed, and non-multiplexed modes).
2
TxMUXEN
R/W
0
Multiplexed Mode Enable
This bit enables or disables the multiplexed mode. When multiplexed mode is
enable, multiplexed data of four channels at 12.352 or 16.384MHz are demul-
tiplexed inside the transmit framer and sent to 4 channels on the line side. The
backplane speed will be running at either 12.352 or 16.384MHz depending on
the multiplexed mode selected by TxIMODE[1:0] of this register.
0 = Disables the multiplexed mode.
1 = Enables the multiplexed mode.
TABLE 30: TRANSMIT INTERFACE CONTROL REGISTER (TICR)
HEX ADDRESS:0Xn120
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
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