REV. 1.0.0 2.10.1 Auto CTS/DSR Flow Control Automatic CTS/DSR flow con" />
參數(shù)資料
型號: XR16M598IQ100-F
廠商: Exar Corporation
文件頁數(shù): 8/58頁
文件大?。?/td> 0K
描述: IC UART FIFO 16B OCTAL 100QFP
標(biāo)準(zhǔn)包裝: 66
特點(diǎn): *
通道數(shù): 8
FIFO's: 16 字節(jié)
規(guī)程: RS485
電源電壓: 1.62 V ~ 3.63 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 100-BQFP
供應(yīng)商設(shè)備封裝: 100-QFP(14x20)
包裝: 托盤
XR16M598
16
1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 16-BYTE FIFO
REV. 1.0.0
2.10.1
Auto CTS/DSR Flow Control
Automatic CTS/DSR flow control is used to prevent data overrun to the remote receiver FIFO. The CTS/DSR
pin is monitored to suspend/restart local transmitter. The flow control features are individually selected to fit
specific application requirement (see Figure 9):
Select CTS (and RTS) or DSR (and DTR) through MCR bit-2.
Enable auto CTS/DSR flow control using EFR bit-7.
With the Auto CTS or Auto DTR function enabled, the UART will suspend transmission as soon as the stop bit
of the character in the Transmit Shift Register has been shifted out. Transmission is resumed after the CTS#/
DTR# input is re-asserted (LOW), indicating more data may be sent.
If used, enable CTS/DSR interrupt through IER bit-7 (after setting EFR bit-4). The UART issues an interrupt
when the CTS#/DSR# pin makes a transition: ISR bit-5 will be set to a logic 1, and UART will suspend TX
transmissions as soon as the stop bit of the character in process is shifted out. Transmission is resumed
after the CTS#/DSR# input returns LOW, indicating more data may be sent.
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