REV. 1.0.0 ] TABLE
參數(shù)資料
型號(hào)： XR16M598IQ100-F
廠商： Exar Corporation
文件頁數(shù)： 30/58頁
文件大小： 0K
描述： IC UART FIFO 16B OCTAL 100QFP
標(biāo)準(zhǔn)包裝： 66
特點(diǎn)： *
通道數(shù)： 8
FIFO's： 16 字節(jié)
規(guī)程： RS485
電源電壓： 1.62 V ~ 3.63 V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
安裝類型： 表面貼裝
封裝/外殼： 100-BQFP
供應(yīng)商設(shè)備封裝： 100-QFP（14x20）
包裝： 托盤
XR16M598
36
1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 16-BYTE FIFO
REV. 1.0.0
]
TABLE 14: INTERRUPT SOURCE AND PRIORITY LEVEL
PRIORITY
ISR REGISTER STATUS BITS
SOURCE OF THE INTERRUPT
LEVEL
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
1
0
1
0
LSR (Receiver Line Status Register)
2
0
1
0
RXRDY (Received Data Ready)
3
0
1
0
RXRDY (Receive Data Time-out)
4
0
1
0
TXRDY (Transmitter Holding Register Empty)
5
0
MSR (Modem Status Register)
6
0
1
0
RXRDY (Received Xon/Xoff or Special character)
7
1
0
CTS#/DSR#, RTS#/DTR# change of state
X
0
1
None (default) or wake-up indicator
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
ISR[5]: RTS#/CTS# Interrupt Status
This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-5 indicates that the CTS# or RTS# has changed
state from LOW to HIGH.
ISR[4]: Xoff/Xon or Special Character Interrupt Status
This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates that the receiver detected a data match
of the Xoff character(s). If this is an Xoff/Xon interrupt, it can be cleared by a read to the ISR. Reading the
XCHAR register will indicate which character (Xoff or Xon) was received last. If it is a special character
interrupt, it can be cleared by reading ISR or it will automatically clear after the next character is received.
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Table 14). See “Section
ISR[0]: Interrupt Status
Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending. (default condition)
4.5
FIFO Control Register (FCR) - Write Only
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
select the DMA mode. The DMA, and FIFO modes are defined as follows:
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO crosses the trigger level. Table 15 shows the complete selections.
Note that the receiver and the transmitter cannot use different trigger tables. Whichever selection is made last
applies to both the RX and TX side.
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