REV. 1.0.0 2.3 Simultaneous Write to All Channels During " />
參數(shù)資料
型號(hào)： XR16M598IQ100-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 57/58頁(yè)
文件大?。?/td> 0K
描述： IC UART FIFO 16B OCTAL 100QFP
標(biāo)準(zhǔn)包裝： 66
特點(diǎn)： *
通道數(shù)： 8
FIFO's： 16 字節(jié)
規(guī)程： RS485
電源電壓： 1.62 V ~ 3.63 V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
安裝類(lèi)型： 表面貼裝
封裝/外殼： 100-BQFP
供應(yīng)商設(shè)備封裝： 100-QFP（14x20）
包裝： 托盤(pán)
XR16M598
8
1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 16-BYTE FIFO
REV. 1.0.0
2.3
Simultaneous Write to All Channels
During a write cycle, the setting of the Device Configuration register REGB (See Table 9) bit-0 to a logic 1 will
override the channel selection of address A6:A4 and allow a simultaneous write to all 8 UART channels when
any channel is written to. This functional capability allow the registers in all 8 UART channels to be modified
concurrently, saving individual channel initialization time. Caution should be considered, however, when using
this capability. Any in-process serial data transfer may be disrupted by changing an active channel’s mode.
2.4
INT# Ouput
The INT# interrupt output changes according to the operating mode and enhanced features setup. Table 3
and 4 summarize the operating behavior for the transmitter and receiver.
TABLE 3: INT# PIN OPERATION FOR TRANSMITTER
Auto RS485
Mode
FCR BIT-0 = 0
(FIFO DISABLED)
FCR BIT-0 = 1
(FIFO ENABLED)
NO
HIGH = a byte in THR
LOW = THR empty
HIGH = FIFO above trigger level
LOW = FIFO below trigger level or FIFO empty
YES
HIGH = a byte in THR
LOW = transmitter empty
HIGH = FIFO above trigger level
LOW = FIFO below trigger level or transmitter empty
TABLE 4: INT# PIN OPERATION FOR RECEIVER
FCR BIT-0 = 0
(FIFO DISABLED)
FCR BIT-0 = 1
(FIFO ENABLED)
HIGH = no data
LOW = 1 byte
HIGH = FIFO below trigger level
LOW = FIFO above trigger level
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