REV. 1.0.0 3.1.5 RESET [7:0] (default 0x00) Ch-6 Ch-7 Ch-5 Ch-4 Ch-3 C" />
參數資料
型號： XR16M598IQ100-F
廠商： Exar Corporation
文件頁數： 24/58頁
文件大小： 0K
描述： IC UART FIFO 16B OCTAL 100QFP
標準包裝： 66
特點： *
通道數： 8
FIFO's： 16 字節(jié)
規(guī)程： RS485
電源電壓： 1.62 V ~ 3.63 V
帶自動流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶調制解調器控制功能： 是
安裝類型： 表面貼裝
封裝/外殼： 100-BQFP
供應商設備封裝： 100-QFP（14x20）
包裝： 托盤
XR16M598
30
1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 16-BYTE FIFO
REV. 1.0.0
3.1.5
RESET [7:0] (default 0x00)
Ch-6
Ch-7
Ch-5 Ch-4 Ch-3 Ch-2 Ch-1 Ch-0
RESET Register
Individual UART Channel Reset Enable
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
The 8-bit RESET register provides the software with the ability to reset the UART(s) when there is a need.
Each bit is self-resetting after it is written a logic 1 to perform a reset to that channel. All registers in that
channel will be reset to the default condition, see Table 19 for details. As an example, bit-0 =1 resets UART
channel 0 with bit-7=1 resets channel 7.
3.1.6
SLEEP [7:0] (default 0x00)
The 8-bit Sleep register enables each UART separately to enter Sleep mode. Sleep mode reduces power
consumption when the system needs to put the UART(s) to idle. The UART enters sleep mode when there is
no interrupt pending. When all 8 UARTs are put to sleep, the on-chip oscillator shuts off to further conserve
power. In this case, the octal UART is awaken by any of the UART channels from a receive data byte or a
change on any of the modem inputs (CTS#, DSR#, CD#, RI#). The UART is ready after 32 crystal clocks to
ensure full functionality. Also, a special interrupt is generated with an indication of no pending interrupt. Logic 0
(default) and logic 1 disable and enable sleep mode respectively.
Ch-6
Ch-7
Ch-5 Ch-4 Ch-3 Ch-2 Ch-1 Ch-0
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
SLEEP Register
Individual UART Channel Sleep Enable
3.1.7
Device Identification and Revision
There are 2 internal registers that provide device identification and revision, DVID and DREV registers. The 8-
bit content in the DVID register provides device identification. A return value of 0x58 from this register indicates
the device is a XR16M598. The DREV register returns a 8-bit value of 0x01 for revision A, 0x02 for revision B
and so on. This information is very useful to the software driver for identifying which device it is communicating
with and to keep up with revision changes.
3.1.7.1
DVID [7:0] (default 0x44)
Device identification for the type of UART. The Device ID for the M598 is 0x58.
3.1.7.2
DREV [7:0] (default (0x01)
Revision number of the XR16M598. A 0x01 represents "revision-A" with 0x02 for rev-B and so forth.
3.1.8
REGB [7:0] (default 0x00)
REGB[0]: Simultaneous write to all 8 UARTs
Logic 0 = Write to each UART configuration register individually (default).
Logic 1 = Enable simultaneous write to all 8 UART configuration registers. This can be very useful during
device initialization in the power-up and reset routines.
REGB[7:1]: Reserved.
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