TABLE 9: DEVICE CO" />
參數(shù)資料
型號： XR16M598IQ100-F
廠商： Exar Corporation
文件頁數(shù)： 18/58頁
文件大小： 0K
描述： IC UART FIFO 16B OCTAL 100QFP
標(biāo)準(zhǔn)包裝： 66
特點(diǎn)： *
通道數(shù)： 8
FIFO's： 16 字節(jié)
規(guī)程： RS485
電源電壓： 1.62 V ~ 3.63 V
帶自動流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
安裝類型： 表面貼裝
封裝/外殼： 100-BQFP
供應(yīng)商設(shè)備封裝： 100-QFP（14x20）
包裝： 托盤
TABLE 9: DEVICE CONFIGURATION REGISTERS
ADDRESS READ/
WRITE
REGISTER
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x80
R
INT Source
UART 7
UART 6
UART 5
UART 4
UART 3
UART 2
UART 1
UART 0
0x81
R
INT 1
UART 2
bit 1
source
bit 0
UART 1
bit 2
interrupt
bit 1
source
bit 0
UART 0
bit 2
interrupt
bit 1
source
bit 0
0x82
R
INT 2
UART 5
bit 0
UART 4
bit 2
interrupt
bit 1
source
bit 0
UART 3
bit 2
interrupt
bit 1
source
bit 0
UART 2
bit 2
0x83
R
INT 3
UART 7
bit 2
interrupt
bit 1
source
bit 0
UART 6
bit 2
interrupt
bit 1
source
bit 0
UART 5
bit 2
source
bit 1
0x84
R/W
TIMER
CTRL
0
TimerCtrl
bit-3
TimerCtrl
bit-2
TimerCtrl
bit-1
TimerCtrl
bit-0
0x85
R
TIMER
0
0x86
R/W TIMER LSB
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0x87
R/W
TIMER
MSB
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0x88
R/W
8X MODE
UART 7
UART 6
UART 5
UART 4
UART 3
UART 2
UART 1
UART 0
0x89
R/W
4X MODE
UART 7
UART 6
UART 5
UART 4
UART 3
UART 2
UART 1
UART 0
0x8A
W
RESET
Reset
UART 7
Reset
UART 6
Reset
UART 5
Reset
UART 4
Reset
UART 3
Reset
UART 2
Reset
UART 1
Reset
UART 0
0x8B
R/W
SLEEP
Enable
sleep
UART 7
Enable
sleep
UART 6
Enable
sleep
UART 5
Enable
sleep
UART 4
Enable
sleep
UART 3
Enable
sleep
UART 2
Enable
sleep
UART 1
Enable
sleep
UART 0
0x8C
R
DREV
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0x8D
R
DVID
0
1
0
1
0
0x8E
R/W
REGB
0
write to all
UARTs
XR16M598
25
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 16-BYTE FIFO
3.1.1
The Global Interrupt Source Registers
The XR16M598 has a global interrupt source register set that consists of 4 consecutive registers [INT0, INT1,
INT2 and INT3]. The four registers are in the device configuration register address space.
INT3
[0x00]
INT2
[0x00]
INT1
[0x00]
INT0
[0x00]
All four registers default to logic zero (as indicated in square braces) for no interrupt pending. All 8 channel
interrupts are enabled or disabled in each channel’s IER register. INT0 shows individual status for each
channel while INT1, INT2 and INT3 show the details of the source of each channel’s interrupt with its unique 3-
bit encoding. Figure 13 shows the 4 interrupt registers in sequence for clarity. The 16-bit timer and sleep
wake-up interrupts are masked in the device configuration registers, TIMERCNTL and SLEEP. An interrupt is
generated (if enabled) by the 598 when awakened from sleep if all 8 channels were placed in the sleep mode
previously.
[A7:A0]
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