參數(shù)資料
型號： XC6SLX100T-3FG484I
廠商： Xilinx Inc
文件頁數(shù)： 60/89頁
文件大小： 0K
描述： IC FPGA SPARTAN 6 484FGGBGA
標準包裝： 60
系列： Spartan® 6 LXT
LAB/CLB數(shù)： 7911
邏輯元件/單元數(shù)： 101261
RAM 位總計： 4939776
輸入/輸出數(shù)： 296
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 484-BBGA
供應(yīng)商設(shè)備封裝： 484-FBGA
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
DS162 (v3.0) October 17, 2011
Product Specification
63
Spread Spectrum
FCLKIN_FIXED_SPREAD_
SPECTRUM
Frequency of the CLKIN input for
fixed spread spectrum
(SPREAD_SPECTRUM =
CENTER_LOW_SPREAD/
CENTER_HIGH_SPREAD)
30
200
30
200
30
200
30
200
MHz
TCENTER_LOW_SPREAD(6)
Spread at the CLKFX output for
fixed spread spectrum
(SPREAD_SPECTRUM =
CENTER_LOW_SPREAD)
Maximum = 250
ps
TCENTER_HIGH_SPREAD(6)
Spread at the CLKFX output for
fixed spread spectrum
(SPREAD_SPECTRUM=
CENTER_HIGH_SPREAD)
Maximum = 400
ps
FMOD_FIXED_SPREAD_
SPECTRUM
Average modulation frequency
when using fixed spread
spectrum
(SPREAD_SPECTRUM =
CENTER_LOW_SPREAD /
CENTER_HIGH_SPREAD)
Typical = FIN/1024
MHz
Notes:
1.
The values in this table are based on the operating conditions described in Table 2 and Table 55.
2.
For optimal jitter tolerance and a faster LOCK time, use the CLKIN_PERIOD attribute.
3.
Output jitter is characterized with no input jitter. Output jitter strongly depends on the environment, including the number of SSOs, the output drive
strength, CLB utilization, CLB switching activities, switching frequency, power supply, and PCB design. The actual maximum output jitter depends on
the system application.
4.
The CLKFX, CLKFXDV, and CLKFX180 outputs have a duty cycle of approximately 50%.
5.
Some duty-cycle and alignment specifications include a percentage of the CLKFX output period. For example, this data sheet specifies a maximum
CLKFX jitter of ±(1% of CLKFX period + 200 ps). Assuming that the CLKFX output frequency is 100 MHz, the equivalent CLKFX period is 10 ns, and
1% of 10 ns is 0.1 ns or 100 ps. Accordingly, the maximum jitter is ±(100 ps + 200 ps) = ±300 ps.
6.
When using CENTER_LOW_SPREAD, CENTER_HIGH_SPREAD, the valid values for CLKFX_MULTIPLY are limited to 2 through 32, and the valid
values for CLKFX_DIVIDE are limited to 1 through 4.
Table 58: Recommended Operating Conditions for the Phase-Shift Clock in Variable Phase Mode (DCM_SP) or
Dynamic Frequency Synthesis (DCM_CLKGEN)
Symbol
Description
Speed Grade
Units
-3
-3N
-2
-1L
Min
Max
Min
Max
Min
Max
Min
Max
Operating Frequency Ranges
PSCLK_FREQ
Frequency for the PSCLK
(DCM_SP) or PROGCLK
(DCM_CLKGEN) input.
1
167
1
167
1
167
1
100
MHz
Input Pulse Requirements
PSCLK_PULSE
PSCLK (DCM_SP) or PROGCLK
(DCM_CLKGEN) pulse width as a
percentage of the clock period.
40
60
40
60
40
60
40
60
%
Table 57: Switching Characteristics for the Digital Frequency Synthesizer DFS (DCM_CLKGEN)(1) (Cont’d)
Symbol
Description
Speed Grade
Units
-3
-3N
-2
-1L
Min
Max
Min
Max
Min
Max
Min
Max
Typical
100
CLKFX_DIVIDE
------------------------------------------
=
Typical
240
CLKFX_DIVIDE
------------------------------------------
=
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