參數(shù)資料
型號(hào)： XC6SLX100T-3FG484I
廠商： Xilinx Inc
文件頁(yè)數(shù)： 51/89頁(yè)
文件大?。?/td> 0K
描述： IC FPGA SPARTAN 6 484FGGBGA
標(biāo)準(zhǔn)包裝： 60
系列： Spartan® 6 LXT
LAB/CLB數(shù)： 7911
邏輯元件/單元數(shù)： 101261
RAM 位總計(jì)： 4939776
輸入/輸出數(shù)： 296
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 484-BBGA
供應(yīng)商設(shè)備封裝： 484-FBGA
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
DS162 (v3.0) October 17, 2011
Product Specification
55
BPI Master Flash Mode Programming Switching(4)
TBPICCO(5)
A[25:0], FCS_B, FOE_B, FWE_B, LDC outputs valid
after CCLK falling edge
15
20
ns, Max
TBPIICCK
Master BPI CCLK (output) delay
10/100
10/130
s, Min/Max
TBPIDCC/TBPICCD
Setup/Hold on D[15:0] data input pins
5.0/1.0
6.0/2.0
ns, Min
SPI Master Flash Mode Programming Switching(6)
TSPIDCC/TSPIDCCD
DIN, MISO0, MISO1, MISO2, MISO3, Setup/Hold
before/after the rising CCLK edge
5.0/1.0
7.0/1.0
ns, Min
TSPIICCK
Master SPI CCLK (output) delay
0.4/7.0
0.4/10.0 s, Min/Max
TSPICCM
MOSI clock to out
13
19
ns, Max
TSPICCFC
CSO_B clock to out
16
26
ns, Max
CCLK Output (Master Modes)
TMCCKL
Master CCLK clock duty cycle Low
40/60
%, Min/Max
TMCCKH
Master CCLK clock duty cycle High
40/60
%, Min/Max
FMCCK
Maximum frequency, serial mode (Master Serial/SPI)
All devices
40
30
MHz, Max
Maximum frequency, parallel mode (Master
SelectMAP/BPI)
LX9, LX16, LX25, LX25T, LX45, LX45T, LX75, and
LX75T
40
25
MHz, Max
Maximum frequency, parallel mode (Master
SelectMAP/BPI)
LX100 and LX100T in x8 mode, LX150, and LX150T
40
20
MHz, Max
Maximum frequency, parallel mode (Master
SelectMAP/BPI)
LX100 and LX100T in x16 mode
35
20
MHz, Max
FMCCKTOL
Frequency Tolerance, master mode
±50
%
CCLK Input (Slave Modes)
TSCCKL
Slave CCLK clock minimum Low time
5
8
ns, Min
TSCCKH
Slave CCLK clock minimum High time
5
8
ns, Min
USERCCLK Input
TUSERCCLKL
USERCCLK clock minimum Low time
12
16
ns, Min
TUSERCCLKH
USERCCLK clock minimum High time
12
16
ns, Min
FUSERCCLK
Maximum USERCCLK frequency
40
30
MHz, Max
Notes:
1.
Maximum frequency and setup/hold timing parameters are for 3.3V and 2.5V configuration voltages.
2.
To support longer delays in configuration, use the design solutions described in UG380: Spartan-6 FPGA Configuration User Guide.
3.
Table 6 specifies the power supply ramp time.
4.
BPI mode is not supported in:
LX4, LX25, or LX25T devices
LX9 devices in the TQG144 package
LX9 or LX16 devices in the CPG196 package.
5.
Only during configuration, the last edge is determined by a weak pull-up/pull-down resistor in the I/O.
6.
Defense-grade Spartan-6Q -2Q devices configure in single default SPI Master (x1) mode at Tj = –55°C. During operation and when using all other
configuration functions, the minimum operating temperature is –40°C.
Table 47: Configuration Switching Characteristics(1) (Cont’d)
Symbol
Description
Speed Grade
Units
-3
-3N
-2
-1L
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