- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4246 > XC6SLX100T-3FG484I (Xilinx Inc)IC FPGA SPARTAN 6 484FGGBGA PDF資料下載
參數(shù)資料
| 型號： | XC6SLX100T-3FG484I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 30/89頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA SPARTAN 6 484FGGBGA |
| 標準包裝： | 60 |
| 系列： | Spartan® 6 LXT |
| LAB/CLB數(shù)： | 7911 |
| 邏輯元件/單元數(shù)： | 101261 |
| RAM 位總計： | 4939776 |
| 輸入/輸出數(shù)： | 296 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 484-BBGA |
| 供應商設備封裝： | 484-FBGA |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁當前第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
DS162 (v3.0) October 17, 2011
Product Specification
36
Simultaneously Switching Outputs
Due to package electrical parasitics, a given package supports a limited number of simultaneous switching outputs (SSOs)
when using fast, high-drive outputs. Table 33 and Table 34 provide guidelines for the recommended maximum allowable
number of SSOs. These guidelines describe the maximum number of user I/O pins of an output signal standard that should
simultaneously switch in the same direction, while maintaining a safe level of switching noise for that particular signal
standard. Meeting these guidelines for the stated test conditions ensures that the FPGA operates free from the adverse
effects of GND and power bounce.
For each device/package combination, Table 33 provides the number of equivalent VCCO/GND pairs per bank. For each
output signal standard and drive strength, Table 34 recommends the maximum number of SSOs, switching in the same
direction, allowed per VCCO/GND pair within an I/O bank. The guidelines are categorized by package style, slew rate, and
output drive current. The number of SSOs are also specified by I/O bank. Multiply the appropriate numbers from each table
to calculate the maximum number of SSOs allowed within an I/O bank. The guidelines assume that all pins within a bank use
the same I/O standard. Exceeding these SSO guidelines can result in increased power or GND bounce, degraded signal
integrity, or increased system jitter. For a given I/O standard, if the SSO limit per pair in Table 34 is greater than the maximum
I/O per pair in Table 33, then there is no SSO limit for the exclusive use of that I/O standard.
The recommended maximum SSO values assume that the FPGA is soldered on a printed circuit board and that the board
uses sound design practices. Due to the additional inductance introduced by the socket, the SSO values do not apply for
FPGAs mounted in sockets. The SSO values assume that the VCCAUX is powered at 3.3V. Setting VCCAUX to 2.5V provides
better SSO characteristics. For more detail, see UG381: Spartan-6 FPGA SelectIO Resources User Guide.
SSTL, Class II, 2.5V
SSTL2_II
25
0
VREF
1.25
SSTL, Class II, 1.5V
SSTL15_II
25
0
VREF
0.75
LVDS (Low-Voltage Differential Signaling), 2.5V & 3.3V
LVDS_25, LVDS_33
100
0
–
BLVDS (Bus LVDS), 2.5V
BLVDS_25
–
Mini-LVDS, 2.5V & 3.3V
MINI_LVDS_25, MINI_LVDS_33
100
0
0(3)
–
RSDS (Reduced Swing Differential Signaling), 2.5V & 3.3V RSDS_25, RSDS_33
100
0
0(3)
–
TMDS (Transition Minimized Differential Signaling), 3.3V
TMDS_33
–
PPDS (Point-to-Point Differential Signaling, 2.5V & 3.3V
PPDS_25, PPDS_33
100
0
–
Notes:
1.
CREF is the capacitance of the probe, nominally 0 pF.
2.
Per PCI specifications.
3.
The value given is the differential output voltage.
4.
See the BLVDS Output Termination section in UG381, Spartan-6 FPGA SelectIO Resources User Guide.
5.
See the TMDS_33 Termination section in UG381, Spartan-6 FPGA SelectIO Resources User Guide.
Table 32: Output Delay Measurement Methodology (Cont’d)
Description
I/O Standard
Attribute
RREF
(
)
CREF(1)
(pF)
VMEAS
(V)
VREF
(V)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 25LC128X-I/ST | IC EEPROM 128KBIT 10MHZ 8TSSOP |
| XC6SLX100T-3FGG484I | IC FPGA SPARTAN 6 101K 484FGGBGA |
| 25LC128XT-I/ST | IC EEPROM 128KBIT 10MHZ 8TSSOP |
| 25AA128XT-I/ST | IC EEPROM 128KBIT 10MHZ 8TSSOP |
| XC4VFX12-10SF363I | IC FPGA VIRTEX-4FX 363FCBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC6SLX100T-3FG676C | 制造商:Xilinx 功能描述:FPGA SPARTAN?-6 FAMILY 101261 CELLS 45NM (CMOS) TECHNOLOGY 1 - Trays 制造商:Xilinx 功能描述:IC FPGA 376 I/O 676FCBGA 制造商:Xilinx 功能描述:IC FPGA SPARTAN 6 101K 676BGA |
| XC6SLX100T-3FG676I | 功能描述:IC FPGA SPARTAN 6 676FGGBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan® 6 LXT 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標準包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計:4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應商設備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XC6SLX100T-3FG900C | 制造商:Xilinx 功能描述:FPGA SPARTAN?-6 FAMILY 101261 CELLS 45NM (CMOS) TECHNOLOGY 1 - Trays 制造商:Xilinx 功能描述:IC FPGA 498 I/O 900FBGA |
| XC6SLX100T-3FG900I | 功能描述:IC FPGA SPARTAN 6 900FGGBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan® 6 LXT 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標準包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計:4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應商設備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XC6SLX100T-3FGG484C | 功能描述:IC FPGA SPARTAN 6 101K 484FGGBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan® 6 LXT 標準包裝:24 系列:ECP2 LAB/CLB數(shù):1500 邏輯元件/單元數(shù):12000 RAM 位總計:226304 輸入/輸出數(shù):131 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:208-BFQFP 供應商設備封裝:208-PQFP（28x28） |
發(fā)布緊急采購，3分鐘左右您將得到回復。