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參數(shù)資料
| 型號： | XA3SD3400A-4FGG676I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 9/58頁 |
| 文件大?。?/td> | 0K |
| 描述： | SPARTAN-3ADSP FPGA 3400K 676FBGA |
| 產(chǎn)品培訓模塊： | Extended Spartan 3A FPGA Family |
| 標準包裝： | 40 |
| 系列： | Spartan®-3A DSP XA |
| LAB/CLB數(shù)： | 5968 |
| 邏輯元件/單元數(shù)： | 53712 |
| RAM 位總計： | 2322432 |
| 輸入/輸出數(shù)： | 469 |
| 門數(shù)： | 3400000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 676-BGA |
| 供應(yīng)商設(shè)備封裝： | 676-FBGA（27x27） |
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XA Spartan-3A DSP Automotive FPGA Family Data Sheet
DS705 (v2.0) April 18, 2011
Product Specification
17
Device DNA Read Endurance
Switching Characteristics
All XA Spartan-3A DSP FPGAs ship in the -4 speed grade. Switching characteristics in this document are designated as
Production, as shown in Table 16.
Production: These specifications are approved once enough production silicon of a particular device family member has
been characterized to provide full correlation between speed files and devices over numerous production lots. There is no
under-reporting of delays, and customers receive formal notification of any subsequent changes.
Software Version Requirements
Production-quality systems must use FPGA designs compiled using a speed file designated as PRODUCTION status.
FPGAs designs using a less mature speed file designation should only be used during system prototyping or pre-production
qualification. FPGA designs with speed files designated as Preview, Advance, or Preliminary should not be used in a
production-quality system.
Whenever a speed file designation changes, as a device matures toward Production status, rerun the latest Xilinx ISE
software on the FPGA design to ensure that the FPGA design incorporates the latest timing information and software
updates.
All parameter limits are representative of worst-case supply voltage and junction temperature conditions. Unless otherwise
noted, the published parameter values apply to all XA Spartan-3A DSP devices. AC and DC characteristics are specified
using the same numbers for both I-Grade and Q-Grade.
Create a Xilinx user account and sign up to receive automatic e-mail notification whenever this data sheet or the associated
user guides are updated.
Sign Up for Alerts on Xilinx.com
Timing parameters and their representative values are selected for inclusion below either because they are important as
general design requirements or they indicate fundamental device performance characteristics. The XA Spartan-3A DSP
FPGA speed files (v1.32), part of the Xilinx Development Software, are the original source for many but not all of the values.
The speed grade designations for these files are shown in Table 16. For more complete, more precise, and worst-case data,
use the values reported by the Xilinx static timing analyzer (TRACE in the Xilinx development software) and back-annotated
to the simulation netlist.
Table 17 provides the recent history of the XA Spartan-3A DSP FPGA speed files.
Table 15: Device DNA Identifier Memory Characteristics
Symbol
Description
Minimum
Units
DNA_CYCLES
Number of READ operations or JTAG ISC_DNA read operations. Unaffected by
HOLD or SHIFT operations.
30,000,000
Read
cycles
Table 16: XA Spartan-3A DSP FPGA v1.32 Speed Grade Designations
Device
Production
XA3SD1800A
-4
XA3SD3400A
-4
Table 17: XA Spartan-3A DSP Speed File Version History
Version
ISE Software Release
Description
1.32
ISE 10.1 SP2
Support for Automotive.
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