參數(shù)資料
型號(hào)： XA3SD3400A-4FGG676I
廠商： Xilinx Inc
文件頁數(shù)： 38/58頁
文件大?。?/td> 0K
描述： SPARTAN-3ADSP FPGA 3400K 676FBGA
產(chǎn)品培訓(xùn)模塊： Extended Spartan 3A FPGA Family
標(biāo)準(zhǔn)包裝： 40
系列： Spartan®-3A DSP XA
LAB/CLB數(shù)： 5968
邏輯元件/單元數(shù)： 53712
RAM 位總計(jì)： 2322432
輸入/輸出數(shù)： 469
門數(shù)： 3400000
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 676-BGA
供應(yīng)商設(shè)備封裝： 676-FBGA（27x27）
XA Spartan-3A DSP Automotive FPGA Family Data Sheet
DS705 (v2.0) April 18, 2011
Product Specification
43
Table 38: Switching Characteristics for the DLL
Symbol
Description
Device
Speed Grade: -4
Units
Min
Max
Output Frequency Ranges
CLKOUT_FREQ_CLK0
Frequency for the CLK0 and CLK180 outputs
All
5
250
MHz
CLKOUT_FREQ_CLK90
Frequency for the CLK90 and CLK270 outputs
5
200
MHz
CLKOUT_FREQ_2X
Frequency for the CLK2X and CLK2X180 outputs
10
334
MHz
CLKOUT_FREQ_DV
Frequency for the CLKDV output
0.3125
166
MHz
Output Clock Jitter(2,3,4)
CLKOUT_PER_JITT_0
Period jitter at the CLK0 output
All
–±100
ps
CLKOUT_PER_JITT_90
Period jitter at the CLK90 output
–±150
ps
CLKOUT_PER_JITT_180
Period jitter at the CLK180 output
–±150
ps
CLKOUT_PER_JITT_270
Period jitter at the CLK270 output
–±150
ps
CLKOUT_PER_JITT_2X
Period jitter at the CLK2X and CLK2X180 outputs
–
±[0.5% of CLKIN
period + 100]
ps
CLKOUT_PER_JITT_DV1
Period jitter at the CLKDV output when performing integer
division
–±150
ps
CLKOUT_PER_JITT_DV2
Period jitter at the CLKDV output when performing non-integer
division
–
±[0.5% of CLKIN
period + 100]
ps
Duty Cycle(4)
CLKOUT_DUTY_CYCLE_
DLL
Duty cycle variation for the CLK0, CLK90, CLK180, CLK270,
CLK2X, CLK2X180, and CLKDV outputs, including the
BUFGMUX and clock tree duty-cycle distortion
All
–
±[1% of CLKIN
period + 350]
ps
Phase Alignment(4)
CLKIN_CLKFB_PHASE
Phase offset between the CLKIN and CLKFB inputs
All
–±150
ps
CLKOUT_PHASE_DLL
Phase offset between DLL outputs
CLK0 to CLK2X
(not CLK2X180)
–
±[1% of CLKIN
period + 100]
ps
All others
–
±[1% of CLKIN
period + 150]
ps
Lock Time
LOCK_DLL(3)
When using the DLL alone: The
time from deassertion at the DCM’s
Reset input to the rising transition
at its LOCKED output. When the
DCM is locked, the CLKIN and
CLKFB signals are in phase
5 MHz
F
CLKIN 15 MHz
All
–5
ms
FCLKIN 15 MHz
–
600
s
Delay Lines
DCM_DELAY_STEP(5)
Finest delay resolution, averaged over all steps
All
15
35
ps
Notes:
1.
The numbers in this table are based on the operating conditions set forth in Table 8 and Table 37.
2.
Indicates the maximum amount of output jitter that the DCM adds to the jitter on the CLKIN input.
3.
For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
4.
Some jitter and duty-cycle specifications include 1% of input clock period or 0.01 UI. For example, the data sheet specifies a maximum jitter
of “±[1% of CLKIN period + 150]”. Assume the CLKIN frequency is 100 MHz. The equivalent CLKIN period is 10 ns and 1% of 10 ns is 0.1 ns
or 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 150 ps] = ±250ps, averaged over all steps.
5.
The typical delay step size is 23 ps.
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